Design considerations for 25 nm MOSFET devices

Abstract

This paper presents the results of a systematic theoretical investigation on scaling gate oxide thickness and the source-drain extension (SDE) junction depth to design high performance MOSFET devices with effective channel lengths near 25 nm. In order to obtain 25 nm MOSFETs, CMOS technologies with 40, 50, and 60 nm gate lengths were designed by scaling SDE junction depth to 14, 20, and 26 nm, respectively. Each technology with the target gate oxide thickness was optimized for an off-state leakage current ∼10 nA/μm for 25 nm devices and the device characteristics were obtained for an equivalent gate oxide thickness of 1, 1.5, and 2 nm. The results show that for a target off-state leakage current of 25 nm devices the magnitude of threshold voltage, sub-threshold slope, and drain-induced barrier lowering increases while the magnitude of drive current decreases with the increase of gate oxide thickness. On the other hand, the variation in the magnitude of threshold voltage, sub-threshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of SDE junction depth 14–26 nm. It is, also, found that the gate delay for 25 nm devices increases with the increase of SDE junction depth. This study, clearly, demonstrates the importance of scaling gate oxide thickness and the SDE junction depth below the presently reported limits to design high performance 25 nm MOSFET devices for low voltage application.