Scaling considerations for high performance 25 nm metal–oxide–semiconductor field effect transistors

Abstract

This article presents a systematic simulation-based study on scaling gate oxide thickness and the source–drain extension junction depth to achieve high performance 25 nm metal–oxide–semiconductor field effect transistor devices for low power operation. In order to obtain the target 25 nm devices, complementary metal–oxide–semiconductor (CMOS) technologies were designed by scaling source–drain extension junction depths to 14, 20, and 26 nm and the corresponding gate lengths to 40, 50, and 60 nm, respectively. Each technology was separately optimized for each value of the equivalent gate oxide thickness 1, 1.5, and 2 nm to achieve the target value of off-state leakage current of about 10 nA/μm for 25 nm devices. The simulation results show that for a low voltage operation of 25 nm devices with a fixed off-state leakage current, the magnitude of threshold voltage, subthreshold slope, and the drain-induced barrier lowering is too high while the magnitude of drive current is too low for gate oxide thickness ⩾1.5 nm. However, the variation in the magnitude of threshold voltage, subthreshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of source–drain extension junction depth between 14 and 26 nm. It is also found that the increase in the gate delay is ⩾12% for 25 nm devices with the source–drain extension junction depth ⩾20 nm compared to the similar devices with a source–drain extension junction depth of about 14 nm. This article demonstrates that the continuous scaling of gate oxide thickness below 1.5 nm and the source–drain extension junction depth below 20 nm is essential for achieving high performance CMOS technologies with 25 nm nominal devices for low power application.