Total ionizing dose hardness analysis of transistors in commercial 180 nm CMOS technology

Abstract

The very large scale integrated (VLSI) circuits become susceptible to soft errors mainly due to exposure to harsh environmental conditions. In this paper, the analysis of total ionizing dose (TID) effects on single gate NMOS, enclosed gate NMOS (ELT NMOS), and single gate PMOS are carried out for 180 nm CMOS technology. The various MOS architectures were exposed to radiation using Cobalt-60 (Co60) radiation source. The charge density distribution at pre-radiation and post-radiation condition for all the three above said structures are observed. It is observed that the threshold voltage shift for the single gate NMOS device is about 25 times more in comparison to the ELT NMOS device after radiation at 30 Å (Å) gate oxide thickness. The transfer characteristics (drain current versus gate to source voltage) of single gate NMOS is compared for TID from 0 krad to 500 krad with a step size of 100 krad at different oxide thicknesses from 15 Å to 75 Å. It is observed that the drain current increases with an increase in total dose in the sub-threshold region for lower gate oxide thickness (15 Å to 45 Å) while with the increase of gate oxide thickness (beyond 60 Å), the drain current increases significantly for the higher gate to source voltage also. The drain saturation current decreases with the increase of oxide thickness from 15 Å to 75 Å. The impact of TID on single gate PMOS is analysed and no significant effect of radiation observed on threshold voltage or leakage current. The leakage current shift is the least for single gate PMOS among the single gate NMOS, ELT NMOS, and single gate PMOS after radiation of 500 krad total dose. The layouts are designed in Cadence virtuoso software and simulated in Visual TCAD software.