Increasing Switching Frequency Research Articles

A High Efficiency Model-Based Adaptive Dead-Time Control Method for GaN HEMTs Considering Nonlinear Junction Capacitors in Triangular Current Mode Operation

Gallium nitride (GaN) high-electron-mobility transistor (HEMT) has the advantages of high switching speed and low ON-resistance, which make it widely used in high-frequency applications to realize high power density. Triangular current mode (TCM) modulation has been used in GaN-based converters to simultaneously achieve high power density and high efficiency through full-range zero voltage switching (ZVS). However, as switching frequency increases, the effect of dead time becomes more significant. Meanwhile, because of the junction capacitors of GaN HEMTs, the optimum dead time changes greatly with the turn-off current. Inappropriate dead time will induce extra loss that goes against the further improvement of power density. In order to minimize the dead-time loss in GaN HEMT-based TCM converter, this article proposes a strategy of adaptive dead-time control. An accurate turn-off transient model is proposed to calculate optimal dead time with consideration of the nonlinear capacitors. Based on this model, a loss model is established to evaluate the effect of dead time involving the short circuit in dead time. A new method of drive signal generation in TCM is proposed to increase the accuracy of dead-time control and reduce the current ripple. By reusing the detection signal in TCM, the adaptive dead-time control is realized without extra sensors. The proposed model is verified by a dual-pulse test, which shows the maximum error between the calculated and the experimental turn-off time is below 3 ns. The proposed adaptive dead-time control is implemented in a GaN HEMT-based boost converter. The experimental results show that the adaptive dead-time control can improve the efficiency over all operation conditions compared with using the fixed dead time, and the total loss is reduced by 26.7% at 800-W load and 70.8% at 50-W load.

A Proposed Fast Charging and High-Power System for Wireless Railway Trains Adopting the Input Voltage Sharing Topology and the Balancing Control Scheme

In this article, we deal with the onboard fast energy conversion system (FECS) that is installed in a wireless railway train (WRT), which receives electrical energy not from the wayside device but from the onboard device when traveling between stations, after getting such energy stored by fast charging during its stopping time at a station. The adopted input-series and output-independent architecture and the interleaving topology can reduce the size and weight of onboard FECS for 1500 V, which is double the operating voltage of the existing 750 V operating voltage. This allows 1200 V class insulated-gate bipolar transistor applications to increase switching frequency and reduce passive component volume. In addition, in order to secure system stability, which is important in any transportation system, a WRT must operate on the basis of simple control. Through a simple and efficient balance control based on a variable current limiter, the input voltage unbalance caused by the input voltage sharing is resolved. Also, it can control charging and discharging based on the energy moving characteristic of the train operation pattern and connection with a high-power energy storage pack. The performance of the onboard FECS at 1500 V with the proposed method is experimentally verified on a 600 kW prototype system.

An Improved Direct Torque Control of Three-Level Dual Inverter Fed Open-Ended Winding Induction Motor Drive Based on Modified Look-Up Table

The induction motor (IM) drive with direct torque control scheme (DTC) turns prominent for industrial applications. However, it retains disadvantage of high torque ripples. The conventional look-up table for DTC scheme is structured with selection of reverse voltage vectors (VVs) when flux and torque errors crosses lower hysteresis boundary condition. This results in higher torque ripples and increase in switching frequency. In this article, modified look-up table for DTC of three-level dual voltage source inverter fed open-ended winding IM drive is proposed, where the VVs selection for lower hysteresis boundary conditions of torque and flux are restructured with null voltage states. The selection of suitable null voltage switching states from the various possible combinations of dual inverter switchings is based on minimization of switching state transitions. To nullify flux instability at zero speed, proper active VVs are placed at hysteresis flux +1 and torque 0 condition in the modified look-up table. These overall effective modifications in the proposed DTC scheme enjoys the benefits of reduction in torque ripple, switching frequency, and stable flux maintenance. The MATLAB simulations and practical investigations are conducted for existing and proposed DTC schemes. From these results, the benefits of the proposed DTC over existing DTC schemes are verified.

Accurate frequency‐domain analysis and hybrid control method for isolated dual active bridge series resonant DC/DC converters

This study proposes an accurate frequency model of dual active bridge series resonant DC/DC converters (DABSRC). Differing from the conventional first harmonic approximation method, the proposed steady-state model considers all the harmonic components, which gives an accurate expression of transferred power and resonant current. Based on the proposed model, a precise soft switching criterion was derived, and the soft switching region was extended. On top of that, a hybrid control strategy combining phase shift modulation and frequency modulation was proposed, to achieve soft switching under wide voltage gain and load variations. Thanks to the extended soft switching region, DABSRC can achieve zero-voltage-switching turn-on at light loads, only with a slight increase in switching frequency, hence improving the efficiency a lot. The accurate frequency model and the hybrid control were validated using a 500 W laboratory prototype. The experiment results showed accurate predictions of the proposed model and significant improvements in light load efficiency over a wide range of input voltages.

Grid‐connected medium‐voltage converters with parallel voltage‐source active filters

Grid-connected medium-voltage converters are typically operated at switching frequencies of several hundred hertz per switch position, requiring bulky and expensive LCL filters in order to meet the harmonic limits given by the grid code. Commonly, semiconductor current derating and increased switching frequencies are used to reduce the LCL-filter costs, leading to a reduced utilisation and efficiency of the converter system. To overcome these disadvantages of conventional converter systems, the presented hybrid converter uses a parallel voltage-source active output filter and thus allows a significant reduction of the passive component demand. The harmonic performance is improved for the operation with small passive filter components, revealing the potential for increasing the utilisation and efficiency of high power medium-voltage converters. As a result, significant reductions of the filter losses and passive components as well as an increased output power are achieved compared to a reference LCL-filter-based converter system.

Carrier-Based Digital PWM and Multirate Technique of a Cascaded H-Bridge Converter for Power Electronic Traction Transformers

In the existing technique for power electronic converters with low switching frequency and multiple cells, the sampling frequency is always set at the same value as the control frequency, and the modulating wave in each cell updates itself when its corresponding carrier reaches its peak and valley. In this paper, this implementation scheme is denoted by asymmetrically sampled-pulsewidth modulation (AS-PWM). It is proven that AS-PWM suffers from three defects: further increase of switching frequency is restricted by the available control period and the total cell number; long modulator delay exists and may bring the control system into instability if high crossover frequency is chosen; and spectrum aliasing toward the digital modulating waves may occur and makes the ac input current distorted. Therefore, another implementation scheme of carrier-based digital PWM is recommended in this paper, which is denoted by multisampled PWM (MS-PWM). In MS-PWM, all of the modulating waves update themselves at the same time. The research presented in this paper is based on a power-electronic traction transformer (PETT), which is made up of a cascaded H-bridge converter and several dc/dc converters. For the consideration of scalability, control, and reliability, a star-connected distributed control system is adopted for the PETT equipment. In order to make full use of this distributed hardware, and to improve the control performance with relatively low requirement toward the digital chips, a universal-type multirate structure is proposed in this paper, which is based on the MS-PWM technique. In the proposed structure, the sampling frequency, control frequency, and modulating-wave updating frequency can be separated from the switching frequency, and each of them can be chosen independently according to the practical control demand and the hardware condition. There is no mutual effect between their selections. The influence of the variation of these three frequencies on the control performance is analyzed as well. At last, experimental results based on a five-cell PETT laboratory prototype with a rated power of 30 kW are provided, and all of them verify the effectiveness and correctness of the proposed algorithms.

A Voltage-Edge-Rate-Limiting Soft-Switching Inverter Based on Auxiliary Resonant Pole

To increase switching frequencies while limiting switching losses in voltage-source inverters, power switches have been made significantly faster with achievable switching times now less than 100 ns. However, faster switches generate larger inverter output voltage edge rates ( ${dv/dt} $ ) and result in deleterious effects in variable-speed drive systems including transient overvoltages at motor terminals, electromagnetic interference, and bearing failures due to microarcs. A common approach for limiting peak ${dv/dt} $ involves using a ${dv/dt} $ filter. However, the ${dv/dt} $ filter introduces extra power losses and increases the overall size and weight of the system. Soft-switching circuits, which were originally developed to reduce switching losses, can help reduce ${dv/dt} $ , but using soft-switching to accurately control ${dv/dt} $ has not been fully explored. In this paper, a new soft-switching circuit, entitled the auxiliary resonant soft-edge pole (ARSEP), is set forth. ARSEP improves the available soft-switching circuits so that ${dv/dt} $ can be accurately controlled through the circuit parameter design. An ARSEP inverter prototype was designed, simulated, and constructed to verify its performance and benefits. Compared to a conventional hard-switched inverter with a ${dv/dt} $ filter, the ARSEP inverter prototype results in a significant reduction in overall power loss, inductor volume, and weight.

Integrated dead‐time compensation and elimination approach for model predictive power control with fixed switching frequency

To solve the problem of variable switching frequency in conventional model predictive power control (MPPC), many modified MPPCs with fixed switching frequency have been proposed. However, as the switching frequency increases, additional current harmonics caused by the dead-time are added into the grid current. In this study, an integrated approach with compensation process and elimination process is proposed to eliminate the adverse effect of dead-time. The elimination process with improving gate signals is applied when the phase current is large enough. In contrast, the compensation process is utilised when the phase current is relatively small and the elimination process is troubled by the misjudgement of the current polarity. The experimental results with different dead-time and active power reference are provided to demonstrate the validity of the integrated approach. The integrated approach can further reduces the total harmonic distortion compared to the pure dead-time compensation approach and almost removes the current harmonics caused by the dead-time. Besides, the static error of the power caused by dead-time is dramatically reduced by utilising the integrated approach.

A Low Gate Turn-OFF Impedance Driver for Suppressing Crosstalk of SiC MOSFET Based on Different Discrete Packages

Because of higher switching speed of silicon carbide MOSFET, the crosstalk in a phase-leg configuration will be more serious, which hinders the increase of switching frequency and lowers the reliability of the power electronic equipment. The displacement current of the gate–drain capacitor and the voltage drop on the common-source inductors can induce the crosstalk. In order to suppress the crosstalk, this paper proposes a novel gate driver, in which two additional capacitors are added to create the low turn-off gate impedance. With this proposed driver, the common-source parasitic inductor can be decoupled from the gate loop and the displacement current of the gate–drain capacitor can be bypassed. In addition, the operating principle and the parameters design are also analyzed. Finally, the crosstalk in the non-Kelvin package and the Kelvin package are tested by experiments, the validity of the analysis and the effectiveness for suppression the crosstalk are proved as well.

A Modified DC Power Electronic Transformer Based on Series Connection of Full-Bridge Converters

This paper proposes a novel dc power electronic transformer (DCPET) topology for locomotive, ac/dc hybrid grid, dc distribution grid, and other isolated medium-voltage and high-power applications. Compared with conventional PET topology, the proposed DCPET has fewer power semiconductor devices and high-frequency isolation transformers, which can improve the power density and reliability. Fault handling or redundancy design can be achieved to further improve the reliability when some dc-dc modules break down. Also, input voltage sharing control can be omitted to simplify the control system and improve the stability. Meanwhile, soft switching is guaranteed for all the switches, which is beneficial to increase switching frequency and improve power density. In this paper, the principle, evolution, and control of the proposed DCPET are respectively presented and studied in detail. Finally, a prototype of the proposed DCPET is built and the experimental results verify the validity and superiority of the proposed topology.

A Closed-Loop Modulation Scheme for Duty Cycle Compensation of PWM Voltage Distortion at High Switching Frequency Inverter

Wide bandgap semiconductors with fast switching speed capability are becoming an enabler to achieve the higher power density design. However, the further increase of switching frequency cannot continuously improve the power quality of ac-side waveforms in dc–ac/ac–dc application. The main reason is the distortion of pulsewidth modulation (PWM) voltage at switching point under high switching frequency. In general, there are two contributors causing PWM voltage distortions in bridge-based topologies. One is the deadtime, which occupies higher ratio in the small duty cycle case under high switching frequency and induces the voltage errors. The other one is the turn- off transient in the small load current or around the zero-crossing point of the ac-side current, because the relatively slow rising slope of the drain–source voltage will affect the right duty cycle. To solve this issue, this paper proposes a closed-loop modulation scheme to compensate the duty cycle distortion of PWM voltage based on one-cycle control or charge control. Compared to the traditional feedforward type of compensation, the proposed scheme does not need online calculation and instantaneous inductor current sampling, and it shows potential to be a general scheme for variety of topologies and modulations. Simulations and experiments are carried out on a 400-kHz single-phase full-bridge inverter with 400-Hz fundamental frequency to demonstrate the performance of the proposed approach.

A Family of Single-Stage High-Gain Dual-Buck Split-Source Inverters

In this paper, a family of single-phase single-stage high-gain dual-buck split-source inverters (SSIs) is proposed. The proposed inverters have the combine benefits of SSI, dual-buck inverter (DBI), and high-gain dc–dc converters. Similar to the DBI, they provide high reliability by eliminating shoot-through issues, increase switching frequency and efficiency by using power MOSFETs without leading the body diodes to reverse recovery issues, and decrease pulsewidth modulation (PWM) dead-time. In addition, voltage boost operation is achieved in a single stage without using any additional active switch, which is in favor of lower control complexity and lower cost. On the other hand similar to the SSI, buck–boost dc–ac power conversion is realized in a single stage. However, compared to the SSI, the proposed inverters have no shoot-through issues, MOSFETs can be used without reverse recovery issues, dead-time can be minimized, switching frequencies can be increased, and external fast recovery diodes can be used to improve efficiency. In addition, four different high-gain dual-buck SSIs are presented. As an example, the proposed switched-coupled-inductor split-source DBI is analyzed and compared with the other proposed structures. To validate the theoretical analysis, a 300-W experimental prototype is designed and tested at 25–35-V input voltage, $155~V_{\text {peak}}$ output voltages and 50 kHz.

DC-DC Converter Design Issues for High-Efficient DC Microgrid

In this article, the electrical properties, as well as the economic aspects of the modular and non-modular solution of the DC-DC photovoltaic converter for DC microgrid subsystem, are described. Principally a theoretical overview of the circuit configuration for the selected DC-DC stage of the DC microgrid system is shown. It is dealt with the comparison of the one non-modular high - voltage SiC-based dual - interleaved converter operating at the low switching frequency and with modular low voltage GaN-based DC-DC converters operating at high switching frequencies. The main focus is given to the research of the dependency that arises from the different module count, overall efficiency, costs, and power density (system volume). High efficiency, reduced overall volume, and maximum power density are important factors within modern and progressive solar systems. It is assumed that with the increase of switching frequency within the modular system the volume reduction of the passive components will be highly demanded, thus PCB dimensions and overall volume can be reduced. This dependency is investigated, while the total volume of the non-modular system is a unit of the measure. For these purposes, the design of variant solution was done, and consequently mutually compared in the way of simulations and experimental measurements.

Reduction of EMI Noise Due to Nonideal Interleaving in a 100 kW SiC PV Converter

A Grid-tied inverter utilizing wide bandgap devices can achieve higher switching frequency resulting in a power filter with reduced size and weight. However, the increased switching frequency may lead to more switching harmonics entering the electromagnetic interference (EMI) frequency range, which will increase the size of EMI filter. Interleaving paralleled converters can cancel some of the switching harmonics and reduce the size of EMI filter. However, nonideal interleaving will deteriorate the harmonic canceling effect. In this research, the nonideal effects are found to be from the small mismatch of the pulsewidth of the interleaving legs and the mismatch of the impedance between the interleaving legs. A modulation method is proposed to completely eliminate the pulsewidth mismatch. Compared with other solutions, the proposed method does not require the information of filter parameters, neither gate driver synchronization, and nor a special function block of the digital controller. The proposed modulation was implemented on a 150 MHz digital signal processor and a 100 MHz field-programmable gate array, and was experimentally verified on a 100 kW parallel coupled SiC PV inverter prototype.

Accurate Operating Analysis of Boundary Mode Totem-Pole Boost PFC Converter Considering the Reverse Recovery of mosfet

The boundary conduction mode (BCM) totem-pole boost power factor correction (PFC) topology is becoming popular in high-efficiency and high power density applications because of its advantages of fewer devices and low conduction losses. The ideal design methodology for the BCM boost converter ignores the reverse recovery of mosfet s’ body diode and the resonance between the inductance and output junction capacitances of switches. However, as the switching frequency increases, these two factors affect the peak value of the inductance current and the switching frequency significantly, which are critical parameters for the boost PFC inductor design. In order to calculate the practical peak current and switching frequency range accurately, this letter proposes an analytical reverse recovery model of the body diode and presents accurate switching cycle operating modes. Either the predicted inductance peak current or the switching frequency range matches the measured result on a 600-W totem-pole boost PFC prototype.

Predictive Current Controller for Single-Phase Grid-Connected VSIs With Compensation for Time-Delay Effect and System Uncertainty

In the last decade, predictive current control (PCC) has been widely implemented for grid-connected voltage source inverters (VSIs) due to the advantages of low-current harmonic injection, fast dynamic response, and easy implementation for digital control systems. However, with the increasing switching frequency of VSIs applied to pursue a better output quality, inevitable time delays and uncertain system disturbances are aggravating system performance and stability, which presents a serious challenge for the PCC design. Thus, a new PCC algorithm has been proposed in this paper for a single-phase VSI to improve the quality of the current fed to the grid, as well as enhance the system stability and robustness. The proposed control scheme is developed from the traditional predictive current controller along with a simple weighted filter predictor and a robust adaptive voltage compensator. The results of simulation and experiment investigation have demonstrated the improvements of the proposed control scheme in inverter output quality and robustness to parameter variations.

Research on Energy Storage Interface Circuit and Its Control Principle Based on the L-LLC Resonant Bidirectional DC-DC Converter

Aiming at the low operating efficiency and poor dynamic response of energy storage interface circuit for flexible interface of connecting microgrid to power grid, the principle of PI or PID and optimal trajectory hybrid control based on the L-LLC resonant bidirectional DC-DC converter (L-LLC BDC) is proposed. It realize zero-voltage switching and zero-current switching for input switches and output rectifiers respectively, besides, it not only significantly reduce the computational complexity and further increase switching frequency, but also improve dynamic response of the converter remarkably. Using state-plane analysis, the operation status and characteristics of L-LLC-BDC are described in detail, based on that, the control system of the energy storage interface circuit is designed. In view of the principle of PI or PID and optimal trajectory hybrid control based on the L-LLC-BDC, the simulation shows that the correctness of theoretical analysis and the superiority of dynamic response and the operation performance of flexible interface of connecting microgrid to power grid is guaranteed.

Stability Analysis and Grid Disturbance Rejection for a 60-kW SiC-Based Filterless Grid-Connected PV Inverter

With increased switching frequency and multilevel topology, it is possible for a wide-bandgap-device-based grid-connected converter to achieve filterless function and utilize the grid impedance for its switching harmonic attenuation. In this paper, a filterless grid-connected SiC inverter is designed and demonstrated. Stability has been analyzed with a focus on grid disturbance rejection. The analysis shows that the conventional control method with instantaneous grid voltage feedforward (IGVF) will significantly limit the bandwidth or stability margin of a filterless grid-connected inverter, thus make the inverter sensitive to grid disturbance. Two grid voltage feedforward control methods, which require little additional computation resources, are proposed to suppress the grid voltage disturbance. The closed form equations for control parameters are derived. The effects of the proposed feedforward methods are also compared with that of conventional IGVF. Finally, the grid-connected experimental results of a 60-kW SiC-based 5-level photovoltaic inverter are provided to verify and compare the proposed control methods.

A Reliable Three-Phase Transformerless Grid-Connected PV Inverter With Inductive DC Link

In this paper, a modified buck–boost grid-connected three-phase photovoltaic inverter is presented. In the structure of inverter, an inductive dc link is used between the input and output. The merits of the employed inverter are soft switching and step-up/down conversion without any additional power converter stage. It is a transformerless inverter with no leakage current issue. Moreover, as a result of increased switching frequency, it offers output current total harmonic distortion within standard limits. It uses only one current sensor and there is no electrolytic capacitor in it, which leads to high reliability. The operating principle is thoroughly explained and a simple control strategy with a new maximum power point tracking (MPPT) algorithm is proposed. The simulation and experimental results are provided to verify the behavior of a modified inverter, its control strategy, and the MPPT method.

Integrated Very-High-Frequency Switch Mode Power Supplies: Design Considerations

This paper presents a power supply using an increased switching frequency to minimize the size of energy storing components, thereby addressing the demands for increased power densities in power supplies, and 100-MHz and higher switching frequencies have been used in resonant power converters, which along with the possible integration of passive components on silicon wafer present a beneficial solution in applications such as mobile phones. This paper presents a design for a 9-W class E resonant power converter in a 0.18- $\mu \text{m}$ CMOS process. The converter is driven by a self-oscillating gate drive, which is presented in an in-depth mathematical analysis. The gate resistance of the designed transistors is of critical importance in order to achieve the correct phase shift required for zero voltage switching. The Z-parameter method is used to characterize the transistors, which is verified through simulations. The required spiral inductors were modeled, and simulations show $Q$ values of as high as 14 at a switching frequency of 250 MHz. Simulations of the converter show an efficiency of 55% with a self-oscillating gate drive. However, the modeled inductor was not adequate for operating with the self-oscillating gate drive, presenting a future challenge for power supplies on chip.