Increase In Power Dissipation Research Articles

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead.

A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.

Molecular reorganization energy in quantum-dot cellular automata switching

We examine the impact of the intrinsic molecular reorganization energy on switching in two-state quantum-dot cellular automata cells. Switching a bit involves an electron transferring between charge centers within the molecule. This, in turn, causes the other atoms in the molecule to rearrange their positions in response. We capture this in a model that treats the electron motion quantum-mechanically but the motion of nuclei semiclassically. This results in a non-linear Hamiltonian for the electron system. Interaction with a thermal environment is included by solving the Lindblad equation for the time-dependent density matrix. The calculated response of a molecule to the local electric field shows hysteresis during switching when the sweep direction is reversed. The relaxation of neighboring nuclei increases the localization of the electron, which provides an intrinsic source of enhanced bistability and single-molecule memory. This comes at the cost of increased power dissipation.

Low Voltage and Low Power Front Panel Design for 12 Lead ECG

The use of portable devices is increasing day by day. Mainly these devices play a vital role in medical field when the doctors are unavailable. In that one of the important emergency medical portable systems is Electro Cardiogram (ECG). ECGs are used to measure the abnormalities of the heart by performing electrical activities. It can be done by attaching electrodes on the body for few minutes. To collect the information from electrodes data acquisition system is used in ECGs or in any biomedical systems. The major challenge in implementing data acquisition system is the increase in power dissipation due to the excessive contact impedance of electrodes. As a solution to this, A CMOS 12 lead ECG data acquisition circuit is designed by using analog multiplexers is proposed in this paper. The proposed system is designed by using improved DTMOS based analog multiplexers and these works with a power supply of ±0.2 V with a dynamic voltage range from 1uv to 200mv with the Power dissipation of 140 nW.

К ВОПРОСУ ОБ ОПРЕДЕЛЕНИИ ЭЛЕКТРИЧЕСКИХ НАГРУЗОК ТРАНСФОРМАТОРНЫХ ПОДСТАНЦИЙ

Relevance The calculation of electrical loads is the basis for choosing the carrying capacity of all elements of the electrical network. An increase in rated loads compared to the necessary ones leads to cost overruns on power transmission lines and an increase in power of transformers, and a decrease in rated loads leads to increased power dissipation in networks, increased heating of conductors and transformers and increased thermal deterioration of their insulation. The reliability of the calculation of electrical loads depends both on the reliability of the calculation coefficients used and on the correctness of the methods used. Therefore, the research and improvement of the calculation of electrical loads in the design of power supply systems is an actual problem. Aim of research To investigate the determination of rated loads of transformer substations, methods of accounting for power dissipation in different modes of operation of the power supply system and methods for determining rated currents of cable lines to transformer substations. To consider the correctness of the use of standard forms for determining electrical loads recommended by regulatory documents. To develop a generalized form of performing calculations of electrical loads of transformer substations, combining the calculation of loads on the side of lower and higher voltages. Research methods To solve the tasks, the definition of electrical loads according to standard forms of regulatory documents is investigated. The methods of accounting for power dissipation in transformers under different operating modes of the power supply system and the determination of rated currents along cable lines to transformer substations are considered. Results The shortcomings of the execution and design of the calculation of electrical loads according to standard forms are revealed: standard forms do not contain information at which values of the heating time constant calculations are performed to determine the rated power of the electrical power load on the side of the lower and higher voltages of transformer substations, do not contain the definition of power dissipation in transformers. Ways of improving the calculation of electrical loads of transformer substations are proposed. A generalized form of execution and design of calculations of electrical loads of transformer substations have been developed, which include the values of time constants when calculating electrical power loads, the type and passport data of the selected transformer, calculations of power dissipation in transformers in two modes and calculations of the load current of cable lines to transformer substations.

Electrical resistance flash sintering of tungsten carbide

This work explores the possibilities for the ultrafast sintering of binderless tungsten carbide by electric/pressure assisted sintering. A limited voltage (3–4 V) in AC condition was applied to WC powder compact in combination with uniaxial pressure. The thermal insulating ceramic die allows the ultrafast heating (104 °C/min) of the powder compact which undergoes a rapid transition of its electrical properties, from negative to positive dependence of resistivity on temperature, i.e. from NTC to PTC behaviour. Such effect is fundamental for inducing a thermal runaway phenomenon associated with ultrarapid temperature increase and massive electric power dissipation, thus inducing very rapid sintering. The relationship between electrical properties of tungsten carbide and the possibility to achieve “flash sintering” conditions to complete densification in a couple of seconds was investigated. At the optimal conditions of 3.5 V and 4 MPa pressure, pure WC sinters up to 95% in less than 10 s. Longer sintering time after the flash improves only slightly the density, despite a significant energetic consumption. It is also shown that if larger pressure is applied, the flash event duration and final density decrease.

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

Experimental study and numerical simulation of the kinetic energy recovery of the mine’s exhaust gas

ABSTRACT In mines, the exhaust gas is mainly discharged from main ventilators in free dissipation state. The effective recovery of its kinetic energy is lucrative from economical and technical standpoints. This study is focused on recovering the kinetic energy of the exhaust gas without deteriorating the main ventilator’s safe operation or increasing power dissipation. The related experiments and numerical simulations were performed for the conical diffusers with diffusing angles of 16° and inlet diameters of 220 and 320 mm, respectively. By examining the start-up and operation states of the wind turbines using inlet collectors with conical, circular arc, and cone-arc shapes, it was found that the wind speed at the inlet of the drainage tube exceeded 4 and 20 m/s at the minimal and maximal distances from the wind turbine, respectively. The wind speed at the overflow tube outlet was no less than 1.8 m/s, proving a certain recovery of kinetic energy by the wind turbine. Thus, the critical distance between the diffuser and the inlet collector should be at least four times the diffuser’s inlet diameter. Finally, the velocity, pressure, and flow fields in the vortex core regions of the kinetic recovery system with different types of inlet collectors were simulated with the FLUENT commercial software package. The simulation results revealed that the circular-arc collector outperformed other three tested configurations in kinetic energy recovery. Implications: This study is focused on recovering the kinetic energy of the exhaust gas without deteriorating the main ventilator’s safe operation or increasing power dissipation. China is a country with coal as its main energy source, which releases over ten billion cubic meters of the exhaust gas annually. In addition to low-concentration methane, there is also the exhaust gas released at a velocity of about 20 m/s, which kinetic energy recovery would be very lucrative. The significance of this study is that the mine’s main ventilator outlet was simplified as two conical diffusers with parameters α=16°/n=2 and α=16°/n=2.5, and the optimal critical distance between the diffuser and the collector was determined as 4Di , where Di was the diffuser’s inlet diameter. Under that optimal condition, the system can achieve the maximum power without affecting the ventilator’s normal operation. It is instructive to make full use of and manage the exhaust gas in mine that fits the journal on the purpose of air waste management. Finally, we provide a statement serious that the article is original and unpublished and is not being considered for publication elsewhere.

A mathematical programming method for constructing the shortest interconnection VLSI arrays

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.

Performance of liquid-lithium-filled 3D-printed tungsten divertor targets under deuterium loading with ELM-like pulses in Magnum-PSI

A fusion reactor divertor must withstand heat flux densities <10 MW m−2. Additionally, it may have to withstand millisecond pulses on the order of 0.5 to 30 MJ m−2 due to (mitigated) edge-localized modes (ELM) occurring with 30 to 60 Hz. We investigate if these requirements can be met by capillary porous system (CPS) liquid lithium divertors (LLD). 3D-printed tungsten CPS targets were exposed in the linear plasma device Magnum-PSI, to deuterium plasma discharges lasting 15 s, generating 1.5 to 16 MW m−2, and T e ∼ 1.5 eV. Additionally, ELM-like pulses were superimposed on top of the steady state for 3 s with a frequency of 2 and 100 Hz, power flux densities of 0.3 to 1 GW m−2, and T e up to ∼14 eV. All Li targets survived without damage. The surface temperature (T s) was locked at ∼850 °C, which was attributed to power dissipation via vapor shielding. Meanwhile, unfilled reference targets melted during the severest pulsed loading. A blue grayish layer of presumably LiD formed when T s < 500 °C, but disappeared when the locking temperature was reached. This implies that LiD formation can be avoided, but that it may require a surface temperature at which Li evaporation excessively contaminates the core plasma in a tokamak. During pulsed loading the plasma facing surface remained wetted in all conditions. Bolometry indicated that, only during pulses, there was a large increase in radiative power dissipation compared to targets without Li. A high speed camera with a Li-I filter showed that strong Li evaporation continued up to 5 ms after a pulse. Overall, the liquid-lithium-filled 3D-printed tungsten targets were found to be highly robust, and 3D-printing can be considered as a promising manufacturing technique for LLDs. Further research is needed particularly on the formation of LiD and the associated tritium retention, as well as the impact of enhanced evaporation during and after ELMs on the core plasma.

A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction

The irrational coefficients of orthogonal wavelet filters require a large amount of hardware for their implementation. This results in huge memory requirement, increased power dissipation and reduction in speed of operation. This paper presents a new class of multiplier free db3 orthogonal wavelet filter bank with significantly reduced power dissipation, adders and shifters. In this paper, dyadic filter coefficients of db3 have been obtained by slightly altering double-shifting orthogonality property for perfect reconstruction. The proposed db3 wavelet filter improved time–frequency product, Sobolev regularity and frequency selectivity. Also, the VLSI architecture is suggested for the proposed db3 wavelet filter banks to analyse the hardware computational complexity. The performance of the proposed db3 wavelets achieved satisfactory performance for feature extraction in medical image retrieval and fingerprint recognition of infants and toddlers.

High-frequency MnZn soft magnetic ferrite by engineering grain boundaries with multiple-ion doping

MnZn soft magnetic ferrites have been widely utilized in power electronics, owing to the combined merits of high permeability and low energy loss. However, their deployment would result in a drastic increase in power dissipation at >3 MHz, thus limiting the scope extent of miniaturization, together with their efficiency. Here, we report a high-performance MnZn ferrite by doping multiple ions (La, Ti, Si, Ca) at grain boundaries, achieving the most optimized power loss of 267 kW/m3 at 5 MHz (10 m T, 100 °C) and initial permeability of 644, which is much better than the previously reported results and commercial products. Such an improvement is attributed to weakened magnetic exchange coupling at grain-boundary regions, associated with a significant transition from the multi- to mono-domain structures, originating physically from large crystallographic mis-orientations (>25°). The present study bears important significance in understanding the intrinsic correlation between the crystallographic mis-orientation and magnetic domain structure, and provides an alternative way for optimizing high-frequency soft magnetic ferrites.

Design of Arithmetic Logic Unit using Pseudo Dynamic Buffer based Domino Logic

Design of combinational circuits using dynamic logic has the advantage of high speed and less area when compared to conventional CMOS logic. However, it pose problem while cascading dynamic logic architectures and also more prone to leakage current issue. These issues are overcome by using domino logic with static inverter at the output of dynamic node. The increased power dissipation at the output node is reduced by using pseudo dynamic buffer based domino logic by having static like switching at the output node. This paper details the design of arithmetic and logic unit designed using conventional and pseudo dynamic buffer based domino logic. The arithmetic unit comprise adder, subtractor, multiplier and logical unit comprise AND, NAND, OR, NOR and XOR logic blocks based on pseudo dynamic buffer based domino logic and it is compared with the Arithmetic logic unit designed using conventional domino logic. The design and simulations are performed using UMC90nm technology node library using Cadence® Virtuoso® tool. The simulation result of ALU unit demonstrates that arithmetic logic unit designed using PDB logic has reduction in power consumption by 89.14% and delay by 1.995% while compared to conventional domino logic.

Response of Global Tropical Cyclone Activity to Increasing CO2: Results from Downscaling CMIP6 Models

AbstractGlobal models comprising the sixth-generation Coupled Climate Model Intercomparison Project (CMIP6) are downscaled using a very high-resolution but simplified coupled atmosphere–ocean tropical cyclone model, as a means of estimating the response of global tropical cyclone activity to increasing greenhouse gases. As with a previous downscaling of CMIP5 models, the results show an increase in both the frequency and severity of tropical cyclones, robust across the models downscaled, in response to increasing greenhouse gases. The increase is strongly weighted to the Northern Hemisphere, and especially noteworthy is a large increase in the higher latitudes of the North Atlantic. Changes are insignificant in the South Pacific across metrics. Although the largest increases in track density are far from land, substantial increases in global landfalling power dissipation are indicated. The incidence of rapid intensification increases rapidly with warming, as predicted by existing theory. Measures of robustness across downscaled climate models are presented, and comparisons to tropical cyclones explicitly simulated in climate models are discussed.

Design of low power, programmable low-Gm OTAs and Gm-C filters for biomedical applications

In this paper, two programmable operational transconductance amplifiers (POTAs)—one using bulk driven attenuator (BDA) and another using programmable current mirror (PCM) are proposed in order to achieve low-Gm and high dynamic range. These OTAs are denoted as BDA-POTA and PCM-OTA respectively and are realized using composite transistors operated in the subthreshold region. The pseudo resistor is used for achieving programmability in the former and for improving the linearity and dynamic range in the latter. The proposed OTAs and two 4th order programmable Butterworth low pass filters (LPF) are designed and implemented in CMOS 180 nm technology with a supply voltage of 0.9 V. Their performances are evaluated through post-layout simulations and are found to be superior compared to those of POTAs reported in the literature for biomedical applications. The power consumption, transconductance, dynamic range and input-referred noise of BDA-POTA and PCM-OTA are [25.2 nW, (7.89–15.61 nS), (77.54–74.89 dB), (39.86–51.19 µVrms)] and [72.81 nW, (5.49–174.5 nS), (91.20–84.39 dB), (17.19–34.92 µVrms)] respectively. The power dissipation and cut off frequency range of the LPF using BDA-POTA and PCM-OTA are [197.8 nW, (30–100 Hz)] and [209.8 nW, (16–971 Hz)] respectively. The latter achieves 13.6 times wider programmability with only 5% increase in power dissipation. The proposed LPFs have better FOM compared to those reported in the literature.

Taguchi Approach and Response Surface Analysis for Design of a High-performance Single-walled Carbon Nanotube Bundle Interconnects in a Full Adder

In this study, it was attempted to design a high-performance single-walled carbon nanotube (SWCNT) bundle interconnects in a full adder. For this purpose, the circuit performance was investigated using simulation in HSPICE software and considering the technology of 32-nm. Next, the effects of geometric parameters including the diameter of a nanotube, distance between nanotubes in a bundle, and width and length of the bundle were analyzed on the performance of SWCNT bundle interconnects in a full adder using Taguchi approach (TA). The results of Taguchi sensitivity analysis (TSA) showed that the bundle length is the most effective parameter on the circuit performance (about 51% on the power dissipation and 47% on the propagation delay). Moreover, the distance between nanotubes greatly affects the response compared to other parameters. Also, response surface method (RSM) indicated that an increase in the length of interconnects (L) improves the output of power dissipation. As the width of interconnects (W) and diameter of CNTs (D) increase the power dissipation also increases. Decrease in the distance between CNTs in a bundle (d) leads to an increase in power dissipation. The highest value of power dissipation is achieved if the maximum values for the parameters of length and width of interconnects (L, W), and diameter of CNTs (D) and the minimum value of the distance between CNTs in a bundle (d) are considered. It is also revealed that an increase in the length of interconnects (L) increases the propagation delay. Eventually, the optimum parameters are reported and the performance of the optimized system is compared using different methods (TA and RSM). Results indicate that the difference between the performance of optimal design of SWCNT bundle interconnects in a full adder predicted by different methods is less than 6% which is acceptable according to engineering standards.

Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles

The Viterbi Algorithm is a recursive optimal solution for estimating the most likely state sequence of discrete-time finite-state Markov process and Hidden Markov Models (HMM) observed in memoryless noise. The Viterbi algorithm is extensively used for decoding convolutional codes, in the constraint length k that encompasses its use in digital communications specifically in satellite and cellular communications. Storage devices to speed up access, speech synthesis and recognition technologies use the Viterbi algorithm or its variants. In this paper low-power, high-speed and reduced transistor count Viterbi decoding circuits with enhanced error detection capabilities are designed and implemented with signature-based error detection schemes in three design logic styles primarily Conventional CMOS, Hybrid logic and GDI. The significance of the work is the upshot of realizing low latency and low power dissipation with high reliability in the iterative process of finding the least path metric by superseding the subtractor in CSA & PCSA circuits with an optimized comparator. When evaluated against the Traditional/Benchmark CSA & PCSA circuits, the Conventional CMOS design approach attains low power consumption and high accuracy with a reduction in average power dissipation by 4.69% and 3.83% and an improvement in delay performance by 7.89% and 3.79% respectively, with a tradeoff for high area utilization. Whereas, the GDI design approach results in an extreme reduction of transistor count by 71.52% and 74.94% with a weaker logic swing for CSA & PCSA units respectively, complimented by an increase in power dissipation (approximately multiplied by a factor of 5) and deterioration in delay performance by one order of magnitude. The Hybrid logic stages CSA & PCSA units that are 32.52% and 9.27% faster and achieve optimization in area utilization by 48.68% and 51.09% respectively, at the expense of elevated power dissipation by one order of magnitude. All the circuits were designed and simulated using GPDK 90 nm technology libraries on Cadence Design Suite 6.1.6 platform at 27 °C temperature on 1.2 V supply-rail and SPICE codes were generated as well.

SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage

Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, Vddmin, on each die that does not cause SRAM read and write failures, which are majorities of SRAM failures, under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, Vfail, that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM Vˆddmin on each die from the measured Vfail of SRAM monitor on the same die where Vfail-Vddmin correlation table is built-up in design infra development phase, and Vˆddmin can be directly derived from the measured Vfail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 10.45%, read energy by 4.99%, and write energy by 5.45% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint. In addition, the effect of IR drop and process variations of peripheral circuit on Vddmin prediction is taken into account by reflecting them on SRAM bitcell operation. We also solidify our Vddmin prediction methodology by considering the prevention of potential SRAM access failures for high-speed designs as well as the SRAM read and write failures.

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

This paper illustrates the design of low power and high-speed operational Amplifier using Nanoscale Transistors. The proposed design introduces biasing block, for generating I=10uA for Channel length=180nm Technology. Adding biasing block to two-stages operational Amplifier current is constant i.e. there are no fluctuations in power supply, increase in bandwidth and power dissipation is less as compared the previous result. The design is simulated in p-spice tool and performed AC analysis. After analysis, the design achieved the parameter like Gain = 40db, Phase Margin=90º, Unity Gain Band Width=13MHz, Output Swing=0.1v to 1.7v and Power Dissipation=0.145mW.

Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology

AbstractThe reduction in size of metal oxide semiconductor (MOS) devices results in increase in leakage power dissipation, which occurs due to the short‐channel effects in subthreshold region. Now a day's power dissipation is one of the crucial issues that the modern electronic industry is facing. Fin‐type field‐effect transistor (FinFET) can be proven as a best substitute to reduce leakage power dissipation in logic circuits. Degradation of performance with process variations is of major concern and needs to design FinFET circuits with minimum leakage power dissipation. In this paper, static random‐access memory (SRAM) cell is designed using low power shorted‐gate (SG) FinFETs at 7‐nm technology to minimize leakage power dissipation besides improving other performance parameters like static noise margins (SNMs) and power delay product (PDP) as well. The various parameters are analyzed using butterfly and N‐curve methods. The ASAP7 PDK is used to design SRAM cells using Cadence Virtuoso tool. The simulated results show that FinFET input‐dependent (INDEP) technique reduces the leakage power dissipation by 32.08% and 13.50%, respectively, in read and write conditions of FinFET SRAM cell. The Monte‐Carlo simulation results show the reduction in average power using INDEP approach at ±10% process, voltage and temperature (PVT) variations under 3σ Gaussian distribution of FinFET SRAM cell.