Increasing Clock Frequency Research Articles

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

This paper presents a 10 bit charge redistribution successive approximation analog-to-digital converter (ADC) for integrated digitally controlled DC---DC converters. A timing efficient implementation of a window function is proposed, where only a reduced input range is converted. A redundant search is applied to overcome the speed limitation of the analog components. The window mode enables further speed enhancement without an increase of clock frequency and power consumption. Position of the set-point and size of the window is digitally adjustable every conversion. Fabricated in 28 nm low-power CMOS technology the ADC occupies only 110 × 85 µm2. In full range mode a conversion rate of 16 MS/s is achieved and in window mode 26.7 MS/s, respectively. With a measured total power consumption of 710 µW and 9.1 bit ENOB a FOM of 81 fJ/conv-step is reached. A large input range with constant resolution, highly linear characteristic, and high robustness to PVT variations together make this ADC an advantageous alternative to delay line or ring oscillator based window ADCs. The highly digital nature of the proposed architecture allows implementation in modern sub-100 nm CMOS technologies.

Low‐level PGAS computing on many‐core processors with TSHMEM

SummaryDiminishing returns from increased clock frequencies and instruction‐level parallelism have forced computer architects to adopt architectures that exploit wider parallelism through multiple processor cores. While emerging many‐core architectures have progressed at a remarkable rate, concerns arise regarding the performance and productivity of numerous parallel‐programming tools for application development. Development of parallel applications on many‐core processors often requires developers to familiarize themselves with unique characteristics of a target platform while attempting to maximize performance and maintain correctness of their applications. The family of partitioned global address space (PGAS) programming models comprises the current state of the art in balancing performance and programmability. One such PGAS approach is SHMEM, a lightweight, shared‐memory programming library that has demonstrated high performance and productivity potential for parallel‐computing systems with distributed‐memory architectures. In the paper, we present research, design, and analysis of a new SHMEM infrastructure specifically crafted for low‐level PGAS on modern and emerging many‐core processors featuring dozens of cores and more. Our approach (with a new library known as TSHMEM) is investigated and evaluated atop two generations of Tilera architectures, which are among the most sophisticated and scalable many‐core processors to date, and is intended to enable similar libraries atop other architectures now emerging. In developing TSHMEM, we explore design decisions and their impact on parallel performance for the Tilera TILE‐Gx and TILEPro many‐core architectures, and then evaluate the designs and algorithms within TSHMEM through microbenchmarking and applications studies with other communication libraries. Our results with barrier primitives provided by the Tilera libraries show dissimilar performance between the TILE‐Gx and TILEPro; therefore, TSHMEM's barrier design takes an alternative approach and leverages the on‐chip mesh network to provide consistent low‐latency performance. In addition, our experiments with TSHMEM show that naive collective algorithms consistently outperformed linear distributed collective algorithms when executed in an SMP‐centric environment. In leveraging these insights for the design of TSHMEM, our approach outperforms the OpenSHMEM reference implementation, achieves similar to positive performance over OpenMP and OSHMPI atop MPICH, and supports similar libraries in delivering high‐performance parallel computing to emerging many‐core systems. Copyright © 2015 John Wiley & Sons, Ltd.

Low-Pass Delta-Delta-Sigma ADC

The intrinsic low dynamic range of a DC SQUID (<; one flux quantum) usually prohibits its use as a quantizer in a high dynamic range ADC. Here we show a new ADC architecture that incorporates the DC SQUID as a quantizer while enabling dynamic range extension using digital feedback. Using the SQUID as a quantizer, we are able to construct a low pass delta-delta-sigma ADC. To accommodate bipolar signals, a carrier is injected to make the SQUID output voltage at the center of its linear range. The subtraction of carrier before applying digital feedback dominates the latency of the feedback loop measured in clock period. Low feedback latency facilitates higher integrator gain while satisfying the stability criterion, leading to higher LSB, and higher dynamic range. At higher clock frequencies, the increased feedback loop latency necessitates reducing LSB and hence reduced dynamic range. Hence the performance of such ADC does not necessarily scale with increased clock frequency. Here we present performance analysis of such ADC including functional simulation, circuit simulation, and experimental test results.

Coarse Grained Reconfigurable Array Based Architecture for Low Power Real-Time Seizure Detection

There is increasing research and commercial interest in miniature on-body and implantable devices for continuous real-time biosignal monitoring. A key challenge in realizing this vision is in implementation of biosignal processing algorithms with acceptably low energy consumption. In this article, we investigate implementation of the REACT algorithm for real-time epileptic seizure detection on a Coarse Grained Reconfigurable Array (CGRA) based architecture. Computationally expensive biosignal processing tasks are offloaded from a conventional Digital Signal Processor (DSP) to the CGRA. The CGRA is designed to support low power biosignal processing by means of a systolic architecture, flexible interconnect and low resource usage. The CGRA architecture is shown to provide 38% and 60% improvements in energy consumption and in performance, respectively, for the REACT system, without the use of voltage scaling or increased clock frequency.

Pipelined Implementation of Dynamic Rijndael S-Box

architecture for S-Box is proposed in this paper. ROM based look-up table implementation of S-Box requires more memory and introduce unbreakable delay for its access. Pipelined S-Box of combinational logic based implementation gives higher throughput and less delay as compared to that of no pipelined S-Box. 5, 6 and 7 stages of pipelined architecture has been simulated using Xilinx 9.2i for SPARTAN-3 FPGA. The result from Place and Route reports shows increase in maximum clock frequency at the cost of increased number of used slices. However the total delay calculated for the SubByte substitution for large amount of data is reduced considerably. KeywordsAES, S-Box.

Direct wafer bonding of amorphous or densified atomic layer deposited alumina thin films

SOI circuit exhibits excellent performance and rehabilitee but with the component miniaturization trend and the clock frequency increase, the self-heating phenomena that arise from the SOI structure itself must not be underestimated. In order to minimize this problem, several candidates have been identified to replace the buried silicon oxide (SiO2) by high thermal conductive dielectric layers such as HfO2, Si3N4, diamond or Al2O3. In order to elaborate a SOI structure using this kind of innovative buried dielectric, first of all, their direct bonding with silicon has to be studied. In this work, we investigate the bonding thermal behaviour of Si/Al2O3 and Al2O3/Al2O3 direct bonded structures: bondings are submitted to room temperature up to 900 °C annealing. Amorphous or crystallized Al2O3 thin films were used in this study. Bonding energies are measured in an anhydrous atmosphere and bonding defectivity is analysed using scanning acoustic microscope (SAM). With amorphous a-Al2O3 layer, for T > 200 °C, high bonding energy are obtained even if high defect density appeared when annealing temperature exceeded 400---500 °C. Spontaneous debonding phenomena even occurred for a-Al2O3/a-Al2O3 direct bonding. This defectivity, unobservable using infrared camera, may be explained by chemical or structural Al2O3 modification such as gases desorption, internal stress or crystallisation state. Bonding with crystallized Al2O3 film has been also characterized by infrared spectroscopy and complementary analysis. No high defect density is observed with crystallized Al2O3 layer. Based on these results, an Al2O3 bonding mechanism is proposed.

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Wide voltage range operation for DSPs brings more versatility to achieve high energy efficiency in mobile applications. This paper describes a 32 bits DSP fabricated in 28 nm Ultra Thin Body and Box FDSOI technology. Body Biasing Voltage (VBB) scaling from 0 V up to ±2 V decreases the core VDDMIN to 397 mV and increases clock frequency by +400%@500 mV and +114%@1.3 V. The DSP frequency measurements show 2.6 GHz@1.3 V(VDD)@2 V(VBB) and 460 MHz@397 mV(VDD)@2 V(VBB). The lowest peak energy efficiency is measured at 62 pJ/op at 0.53 V. In addition to technological gains, maximum frequency tracking design techniques are proposed for wide voltage range operation. On silicon, at 0.6 V, those techniques allow high energy gain of 40.6% w.r.t. a worst case corner approach.

Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation

Physical models utilize mathematical equations to characterize physical systems like airway mechanics, neuron networks, or chemical reactions. Previous work has shown that field programmable gate arrays (FPGAs) execute physical models efficiently. To improve the implementation of physical models on FPGAs, this article leverages graph theoretic techniques to synthesize physical models onto FPGAs. The first phase maps physical model equations onto a structured virtual processing element (PE) graph using graph theoretic folding techniques. The second phase maps the structured virtual PE graph onto physical PE regions on an FPGA using graph embedding theory. A simulated annealing algorithm is introduced that can map any physical model onto an FPGA regardless of the model's underlying topology. We further extend the simulated annealing approach by leveraging existing graph drawing algorithms to generate the initial placement. Compared to previous work on physical model implementation on FPGAs, embedding increases clock frequency by 25% on average (for applicable topologies), whereas simulated annealing increases frequency by 13% on average. The embedding approach typically produces a circuit whose frequency is limited by the FPGA clock instead of routing. Additionally, complex models that could not previously be routed due to complexity were made routable when using placement constraints.

Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking

Process variation is one of the most important factors to be considered in recent microprocessor design, since it negatively affects performance, power, and yield of microprocessors. However, by leveraging process variation, overclocking techniques can improve performance. As microprocessors have substantial clock cycle time margin for yield, there is enough room for performance improvement by overclocking techniques. In this paper, we adopt the F-overclocking technique, which increases clock frequency without changing supply voltage. Our experimental results show that the F-overclocking technique significantly improves performance as well as energy consumption. In addition, the F-overclocking technique is superior to the conventional overclocking technique which increases clock frequency and supply voltage together in the perspective of energy efficiency and reliability, showing similar performance improvement. Furthermore, we propose an adaptive overclocking controller which dynamically applies the F-overclocking technique based on the application characteristics. By adopting our adaptive overclocking controller, we further minimize the reliability loss caused by the F-overclocking technique.

Clock jitter generator with picoseconds resolution

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220 MHz, a jitter with 4 ps resolution can be injected.

응용프로그램 실행에 따른 CPU/GPU의 온도 및 컴퓨터 시스템의 에너지 효율성 분석

전력 소모 증가와 칩 내부 온도 증가라는 문제점들로 인해 동작 주파수 증대를 통해 CPU의 성능을 향상시키는 기법은 점차 한계에 다다르고 있다. 이와 같은 상황에서, CPU의 작업량을 줄여주는 GPU를 활용하는 것은 컴퓨터 시스템의 성능을 향상시키기 위해 사용되는 대표적인 방안 중 하나이다. GPU는 그래픽 작업을 위해 개발된 프로세서로 기존에는 그래픽 작업들만을 전담으로 처리하여 왔지만, CUDA와 같이 GPU 자원을 쉽게 활용할 수 있는 기술이 점차 개발됨에 따라서 GPU를 범용 연산에 활용함으로써 고성능 컴퓨터 시스템을 구현하는 기법이 주목을 받고 있다. 본 논문에서는 다양한 응용프로그램들을 수행하는 경우에 CPU와 GPU가 동시에 활용되는 고성능 컴퓨터 시스템을 목표로, 시스템에서 발생하는 온도와 에너지 효율성을 상세하게 분석하고자 한다. 이를 통해, CPU와 GPU가 동시에 활용되는 컴퓨터 시스템에서 향후 발생 가능한 온도와 에너지 소비 측면에서의 문제점들을 제시하고자 한다. 온도 분석 결과를 살펴보면, GPU를 이용하여 응용프로그램을 수행하는 경우에는 CPU와 GPU의 온도가 동시에 모두 상승하는 것을 할 수 있다. 이와 달리, CPU를 이용하여 응용프로그램을 수행하는 경우에는 GPU의 온도는 거의 변화가 없이 유지되고, CPU의 온도만이 지속적으로 상승한다. 에너지 효율성 측면에서 살펴보면, GPU를 이용하는 것이 CPU를 이용하는 것과 비교하여 동일한 응용프로그램을 수행하는데 있어서 더 적은 에너지를 소비한다. 하지만, GPU는 CPU에 비해 더 많은 전력을 소모하기 때문에 1Wh의 에너지당 발생하는 온도는 CPU에 비해 GPU에서 훨씬 높게 나타난다. As the clock frequency increases, CPU performance improves continuously. However, power and thermal problems in the CPU become more serious as the clock frequency increases. For this reason, utilizing the GPU to reduce the workload of the CPU becomes one of the most popular methods in recent high-performance computer systems. The GPU is a specialized processor originally designed for graphics processing. Recently, the technologies such as CUDA which utilize the GPU resources more easily become popular, leading to the improved performance of the computer system by utilizing the CPU and GPU simultaneously in executing various kinds of applications. In this work, we analyze the temperature and the energy efficiency of the computer system where the CPU and the GPU are utilized simultaneously, to figure out the possible problems in upcoming high-performance computer systems. According to our experimentation results, the temperature of both CPU and GPU increase when the application is executed on the GPU. When the application is executed on the CPU, CPU temperature increases whereas GPU temperature remains unchanged. The computer system shows better energy efficiency by utilizing the GPU compared to the CPU, because the throughput of the GPU is much higher than that of the CPU. However, the temperature of the system tends to be increased more easily when the application is executed on the GPU, because the GPU consumes more power than the CPU.

병렬 응용프로그램 실행 시 GPU 구조에 따른 성능 분석

통합형셰이더 코어 구조 개발 이후 GPU는 그래픽스 전용 연산장치에서 범용 연산장치로 발달하고 있다. 특히, 병렬 응용 프로그램들은 병렬화된 하드웨어 구조를 효과적으로 활용할 수 있기 때문에, GPU를 활용하여 병렬 응용프로그램들을 실행시키는 기법이 주목을 받고 있다. 하지만, 현재의 GPU 구조는 비그래픽스 응용프로그램을 실행하는데 있어서 병렬성을 충분히 확보하지 못하다는 한계를 가지고 있기 때문에, 이를 해결하기 위해 GPU 구조는 빠르게 변화하고 있다. 본 논문에서는 GPU 구조의 개발 방향을 살펴보기 위해, 비그래픽스 병렬 응용프로그램들을 수행하는 경우에 코어 개수 및 동작 주파수 등의 하드웨어구조에 따른 GPU의 성능을 상세히 분석하고자 한다. 실험 결과, 코어 개수가 30에서 192로 늘어나고 동작주파수가 325MHz에서 450MHz로 증가함에 따라 GPU 성능은 28.9%에서 125.8%, 4.4%에서 16.2% 각각 향상되는 반면 성능 향상 효율성은 감소하는 것을 볼 수 있다. 성능 향상 효율성 감소의 주된 원인은 향상된 연산 능력에 맞추어 증가된 데이터 요구를 메모리가 적절하게 처리하지 못하기 때문이다. 결과적으로 GPU의 성능 향상 효율성을 더욱 높이기 위해서는 연산 능력 향상과 더불어 시스템 자원들 또한 GPU 구조에 맞게 변경되어야 함을 구체적인 실험을 통해 알 수 있다. The role of GPU has evolved from graphics-specific processing to general-purpose processing with the development of unified shader core architecture. Especially, execution methods for general-purpose parallel applications using GPU have been researched intensively, since the parallel hardware architecture can be utilized efficiently when the parallel applications are executed. However, current GPU architecture has limitations in executing general-purpose parallel applications, since the GPU is not specialized for general-purpose computing yet. To improve the GPU performance when general-purpose parallel applications are executed, the GPU architecture should be evolved. In this work, we analyze the GPU performance according to the architecture varying the number of cores and clock frequency. Our simulation results show that the GPU performance improves by up to 125.8% and 16.2% as the number of cores increases and the clock frequency increases, respectively. However, note that the improvement of the GPU performance is saturated even though the number of cores increases and the clock frequency increases continuously, since the data cannot be provided to the GPU due to the limit of memory bandwidth. Consequently, to accomplish high performance effectiveness on GPU, computational resources must be more suitably considered.

Integration of Behavioral Models in the Full-Field TLM Method

The accurate simulation of digital circuits requires the inclusion of field phenomena. Issues such as signal integrity, crosstalk, and external EMI are of paramount importance in the design stage, due to the decreasing feature size and increasing clock frequency of modern digital systems. This paper addresses issues with the incorporation of field phenomena in the simulation of digital systems, by embedding behavioral descriptions of digital ICs into a full wave field model. The paper successfully simulates digital circuits incorporating the external electromagnetic interference (EMI) environment of operation; further research is required to incorporate the internal EMI effects in the IC silicon. The transmission-line modeling method is used for the field model, while the input/output buffer information specification models the digital IC behavior.

Trends and challenges in operating systems—from parallel computing to cloud computing

SUMMARYOver many decades, advances in computer system design and processor manufacturing have resulted in an ever‐increasing per‐chip transistor count, which, in combination with increased clock frequencies, has led to a tremendous increase in single‐thread performance in desktop and server CPUs. The trend to higher integration in processor manufacturing will continue for the next couple of years. However, the increased transistor count leads to additional compute cores within a CPU, rather than to an increased single‐thread performance. Programming and utilizing these future CPUs impose a number of problems commonly referred to as the multicore challenge. These trends primarily affect server computers, whereas on client systems, a break‐even between users' willingness to pay for compute power and today's CPU implementation seems to be reached. In this paper, we argue that the full exploitation of many‐core architectures on the server demands better support by the operating system. This relates to the support of new application programming models, the seamless integration of internal and external services, security, as well as on monitoring and (self‐adaptive) management of such server environments. Within this paper, we discuss three major trends that will drive the adoption of server operating systems to modern many‐core hardware: dynamic parallelism, dynamic partitioning, and dynamic provisioning. Copyright © 2011 John Wiley &amp; Sons, Ltd.

임베디드 병렬 프로세서를 위한 픽셀 서브워드 병렬처리 명령어 구현

프로세서 기술은 공정비용의 증가와 전력 소모 때문에 단순 동작 주파수를 높이는 방법이 아닌 다수의 프로세서를 집적하는 병렬 프로세싱 기술 발전이 이루어지고 있다. 본 논문에서는 멀티미디어에 내재한 무수한 데이터를 효과적으로 처리할 수 있는 SIMD(Single Instruction Multiple Data) 기반 병렬 프로세서를 소개하고, 또한 이러한 SIMD 기반 병렬 프로세서 아키텍처에서 이미지/비디오 픽셀을 효율적으로 처리 가능한 픽셀 서브워드 병렬처리 명령어를 제안한다. 제안하는 픽셀 서브워드 병렬처리 명령어는 48비트 데이터패스 아키텍처에서 4개의 12비트로 분할된 레지스터에 4개의 8비트 픽셀을 저장하고 동시에 처리함으로써 기존의 멀티미디어 전용 명령어에서 발생하는 오버플로우 및 이를 해결하기 위해 사용되는 패킹/언팽킹 수행의 상당한 오버헤드를 줄일 수 있다. 동일한 SIMD 기반 병렬 프로세서 아키텍처에서 모의 실험한 결과, 제안한 픽셀 서브워드 병렬처리 명령어는 baseline 프로그램보다 2.3배의 성능 향상을 보인 반면, 인텔사의 대표적인 멀티미디어 전용 명령어인 MMX 타입 명령어는 baseline 프로그램보다 단지 1.4배의 성능 향상을 보였다. 또한, 제안한 명령어는 baseline 프로그램보다 2.5배의 에너지 효율 향상을 보인 반면, MMX 타입 명령어는 baseline 프로그램보다 단지 1.8배의 에너지 효율 향상을 보였다. Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of <TEX>$2.3{\times}$</TEX> over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only <TEX>$1.4{\times}$</TEX> over the same baseline SIMD array performance. In addition, the proposed instructions achieve <TEX>$2.5{\times}$</TEX> better energy efficiency than the baseline program, while MMX-type instructions achieve only <TEX>$1.8{\times}$</TEX> better energy efficiency than the baseline program.

Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme

Power dissipation has become a critical design constraint for the growth of modern multicore systems due to increasing clock frequencies, leakage currents, and system parasitics. To overcome this urgent crisis, this article presents an embedded platform for on-chip power management of a multicore System-on-Chip (SoC). The design involves the development of two key components, from the hardware to the software level. From the hardware perspective, a multiple-supply power management unit is proposed and is implemented using a Single-Inductor Multiple-Output (SIMO) DC-DC converter. To dynamically respond to the sensed instantaneous power demands and to accurately control the power delivery to the processor cores, the power management unit employs a software-defined adaptive global/local power allocation feedback controller. The proposed controller is designed using the hardware-software codesign methodology to uniquely control the SIMO converter during various operation scenarios. This is achieved using several embedded software control algorithms that operate synergetically to ensure efficient and reliable system operation. The hardware-software codesign technique also allows the SIMO controller to be integrated with future microprocessor cores. Therefore, by employing the vast amount of on-chip resources, the converter can perform effective power processing to provide the most power-optimal voltages at the hardware level. Such an embedded power management module leads to an integrated, power-aware, and autonomous SoC design that is independent of additional external hardware control, thereby reducing on-chip area and system complexity. In this design, each power output from the SIMO converter provides a step-up/down voltage conversion, thereby enabling a wide range of variable supply voltage. An adaptive global/local power allocation control algorithm is employed to significantly improve Dynamic Voltage and Frequency Scaling (DVFS) tracking speed and line/load regulation, while still retaining low cross-regulation. Designed with a 180nm CMOS process, the converter precisely provides three independently variable power outputs from 0.9 V to 3.0 V, with a total power range from 33 mW to 900 mW. A very fast load transient response of 3.25 μ s is achieved, in response to a 67.5-mA full-step load current change. The design thus provides a cost-effective power management solution to achieve a robust, fast-transient, DVFS-compatible multicore SoC.

Effect of Microstructure on Thermal Conductivity of Cu, Ag Thin Films

Thin film type materials are widely used in modern industries, such as semiconductor devices, functional superconductors, machining tools, and so on. The thermal properties of material in semiconductor are very important factors for stable operation because the heat generated during device operation may increase clock frequency. Even though thermal properties of thin films may play a major role in assessing reliability of parts, the measurement methods of thin film thermal properties are generally known to be complex to devise. In this study, a temperature distribution method was applied for the measurement of thermal conductivity of Cu and Ag thin film on borosilicate glass substrate. Cu and Ag thin films were deposited on borosilicate glass using thermal evaporation processes. To measure the thermal conductivity changes according to the microstructure of metallic thin film, the processing variables for the Cu and Ag thin film deposition were changed. To minimize the effect of film thickness, the film thickness was fixed to the thickness of approximately 500 nm throughout experiments. The thermal conductivities of thin films were measured to be much lower than those of bulk materials. Thin film with larger grain size showed higher thermal conductivity probably due to the lower number density of grain boundary. Weidman-Franz law could be applied to thin films produced in this study. Thermal conductivity was also estimated from the resistivity of thin film and Lorenz number of bulk material.

Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions

The shrinking processor feature size, lower threshold voltage, and increasing clock frequency make modern processors highly vulnerable to transient faults. Architectural Vulnerability Factor (AVF) reflects the possibility that a transient fault eventually causes a visible error in the program output, and it indicates a system's susceptibility to transient faults. Therefore, the awareness of the AVF, especially at early design stage, is greatly helpful to achieve a trade-off between system performance and reliability. However, tracking the AVF during program execution is extremely costly, which makes accurate AVF prediction extraordinarily attractive to computer architects. In this paper, we propose to use Boosted Regression Trees (BRT), a nonparametric tree-based predictive modeling scheme, to identify the correlation across workloads, execution phases, and processor configurations between a key processor structure's AVF and various performance metrics. The proposed method not only makes an accurate prediction but also quantitatively illustrates individual performance variable's importance to the AVF. A quantitative comparison between our model and conventional linear regression is performed in terms of model stability, showing that our model is more stable when the model size varies. Moreover, to reduce the prediction complexity, we also utilize a technique named Patient Rule Induction Method (PRIM) to extract some simple selecting rules on important metrics. Applying these rules during runtime can fast identify execution intervals with a relatively high AVF. A case study that enables PRIM-based ROB redundancy has been performed to demonstrate a possible application of the trained PRIM rules.

Realization of BCD adder using ReversibleLogic

This paper proposes novel carry select and carry look-ahead BCD adders using reversible logic. Reversible logic gates are widely known to be compatible with future computing technologies which virtually dissipate zero heat. Adders are fundamental building blocks in many computational units. For this reason, we have simulated several adder circuits using the reversible gates. Among all the other adders, the main virtue of BCD adders is that it allows easy conversion to decimal digits for printing or display and faster decimal calculations. These reversible BCD circuits are basis of the decimal ALU of primitive Quantum CPU. The proposed BCD adders have been simulated in VLSI and static timing report was analyzed. Everyday new technology which is faster, smaller and more complex than its predecessor is being developed. The increase in clock frequency to achieve greater speed and increase in number of transistors packed onto a chip to achieve complexity of a conventional system results in increased power consumption. Almost all the millions of gates used to perform logical operations in a conventional computer are irreversible. That is, every time a logical operation is performed some information about the input is erased or lost and is dissipated as heat. As per Landauer (1), for irreversible logic, each bit of information lost generates kTln2 Joules of heat energy, where k is Boltzmann's constant and T is absolute temperature at which the computation is performed. For room temperature T, the amount of heat dissipated for one bit is small i.e. 2.9×10-21 J (2). The current processors, first of all dissipate 500 times this amount of heat every time a bit is lost. Secondly, assuming every transistor out of more than 4×107 dissipates heat at the processor frequency of 2GHz, the figure becomes 4×1019*kTln2 J/sec. Although, it is around 0.1W at 400 degree Kelvin, Moore's law predicts exponential growth of heat generated due to information loss which will be an intolerable amount in the next decade. This heat dissipation dramatically reduces the performance and lifetime of the circuits. The solution is to use revolutionary technology which enables extremely low power consumption and heat dissipation in computing. Reversible logic, which is an actively researched area, is considered as an apt alternative. The employment of

A single layer zero skew clock routing in X architecture

With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our Planar-CRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.