Modern power electronic technologies relevant to high power and fast switching applications are embracing wide bandgap (WBG) materials, including silicon carbide and gallium nitride (GaN), for their characteristically large breakdown electric field strengths and their comparatively high electron saturation velocities. However, WBG-based structures are known to exhibit unmitigated charge trapping due dangling bonds or impurities at or near the dielectric/semiconductor interface. Interface charge traps with energies near the band edge introduce threshold-voltage instabilities in metal-insulator-semiconductor (MIS) devices. Large densities of interface trap states and surface charges are also known to adversely alter the current response and channel transport dynamics in field effect transistor (FET) devices. Minimizing the density of these performance-degrading features, which are inherent to any MIS gate structure, remains a primary obstacle that prevents WBG-based technologies from realizing their theoretical potential in various application spaces.The complicated nuance of the numerous interface trap characterization techniques reported in literature have made comparing and communicating interface trap results in power electronics research a near-impossible task. As an example, the typical techniques used to characterize the density of interface states in silicon-based systems, such as the high-low method or the Terman method, are not suitable for WBG-based devices since they require unconventionally high probing frequencies to account for the fast trap states associated with WBG materials. Despite this readily proven fact, these techniques are still very popular in the WBG-based power electronics community, and an overwhelming majority of reported interface trap values are therefore unable to be thoughtfully discussed for the betterment of WBG-based technologies. Mitigating charge traps requires repeatable and physically accurate characterization techniques that follow a standard analysis protocol to correlate processing methods with device performance and reliability.Over the last decade, Sandia National Laboratories has made substantial contributions to the development of GaN power semiconductor devices and their characterization. In this talk, we will present recent work conducted at Sandia to develop a standardized procedure for determining interface trap state densities using quasi-static capacitance-voltage analysis in WBG-MIS-capacitor structures that produces repeatable and relatable results. Quasi-static methods that do not require frequency-based capacitance measurements, such as the - technique, have been suggested as a viable solution for determining the interface trap state densities in WBG systems. However, the results produced by the - technique are shown to be susceptible to errors in the analysis procedure and these errors were investigated in detail. These sources of error will be discussed, and we will present new strategies to greatly improve the accuracy of interface trap analysis measurements, including novel techniques to (1) calibrate the surface potential/gate voltage relationship and (2) measure the energy-dependence of capture cross sections. This collection of work greatly simplifies the interface trap analysis procedure and offers a solution to the present obstacle of reporting and comparing interface trap distributions in WBG-MIS structures. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.
Read full abstract