In-order Packet Delivery Research Articles

Leveraging Coupled BBR and Adaptive Packet Scheduling to Boost MPTCP

Multipath TCP (MPTCP) utilizes multiple paths for simultaneous data transmission to enhance performance. However, existing MPTCP protocols are still far from satisfactory in wireless networks because of their loss-based congestion control and the difficulty of managing multiple subflows. To overcome these problems, we redesign the coupled congestion control algorithm and scheduler to boost MPTCP in wireless heterogeneous networks. The main purpose is to promote transmission rate under lossy networks, while also provide stability when networks suffer physical link changes and asymmetric links. In this paper, inspired by Bottleneck Bandwidth and Round-trip propagation time (BBR), we first propose Coupled BBR that utilizes detected bandwidth to adjust the sending rate within an MPTCP connection. Coupled BBR provides high loss tolerance as well as balanced congestion among MPTCP subflows. Then, to further improve the performance, we propose an Adaptively Redundant and Predictive packet (AR&P) scheduler to improve adaptability and keep in-order packet delivery in highly dynamic network scenarios. Based on Linux kernel implementation and experiments in both testbed and real network scenarios, we show that the proposed scheme not only provides high throughput in wireless networks, but also improves robustness and reduces out-of-order packets in some harsh circumstances.

VCS: A method of in-order packet delivery for adaptive NoC routing

Adaptive routing proves its efficiency in sustaining higher network performance bypassing packets through alternate congestion-free minimal or non-minimal routes for a many-core on-chip communication system. It prevents the network from reaching an early saturation due to the stalling of packets in the priority-fixed shortest route for a longer period. However, routing packets adaptively to an alternate route instead of choosing the priority-fixed and shortest route may lead to an unintended state of delivering packets out-of-order sequence at the destination node that is not accepted by many message-passing systems. This ordering mismatch is due to allowing multiple alternate routes for packets of the same communication flow in adaptive mode. In such a case, a packet with a higher sequence number takes over another packet of the same communication flow having a lower sequence number. Storing and reordering all unordered packets of the same communication flow at the sink side becomes costlier due to the increasing area and power requirement. Ideally, the added memory size reaches to infinity for storing all unordered packets that belong to the same communication flow. In the proposed method, we guarantee delivery of all packets belongs to the same communication flow in an orderly manner under adaptive routing mode. In particular, we have proposed a flow-control policy based on a virtual circuit switch (VCS) method that exclusively won and reserve a virtual path for routing packets in an adaptive mode for each communication flow. To maximize network performance, we allow sharing of the reserved path among packets of different communication flows, routing under priority fix deterministic mode. The method saves need of having additional memory unit for storing all unordered packets while guaranteeing the packet’s ordering sequence at the destination end. An experiment conducted on two different size Mesh networks (8x8 and 12x12) under several synthetic traffic and benchmark application reveals that our virtual circuit switching (VCS) based proposed method offers a significant improvement over the state-of-the-art packet reordering method (ROR) and two similar type of research works. Our simulation based experimental result shows that method offers a 60% higher saturation point and 21% improvements (maximum) in throughput while offering a reduction of 60% in NoC area and 58% power value compared to the baseline reorder (ROR) method.

Caterpillar RLNC With Feedback (CRLNC-FB): Reducing Delay in Selective Repeat ARQ Through Coding

Wireless networks typically employ some form of forward error correction (FEC) coding and some automatic repeat request (ARQ) protocol to ensure reliable data transmission over lossy channels. We propose to integrate FEC and ARQ in the context of random linear network coding (RLNC). In particular, we develop Caterpillar RLNC with feedback (CRLNC-FB), an RLNC approach with a finite sliding packet transmission window in conjunction with feedback-based selective repeat ARQ. CRLNC-FB employs a novel RLNC decoding method based on a band-form of Gaussian elimination. In response to lost packets, CRLNC-FB retransmits lost packets in systematic (uncoded) form to aid fast in-order packet delivery at the receiver. Extensive performance evaluations indicate that CRLNC-FB gives higher throughput-delay performance than the preceding RLNC approaches with feedback. In particular, CRLNC-FB with its sliding window achieves lower delays than block-based RLNC. Also, the retransmission of uncoded source packets in CRLNC-FB contributes to a significantly higher throughput-delay performance than loss recovery through coded packets interspersed among future source packets at a prescribed code rate.

On Using Dual Interfaces With Network Coding for Delivery Delay Reduction

This paper considers a heterogeneous network architecture wherein devices use two wireless interfaces to receive packets from the base station and to transmit or receive packets from other devices concurrently. For such a network architecture, this paper focuses on time-critical and order-constrained applications that require quick and reliable in-order decoding of the packets. This paper first introduces the dual delivery delay as a measure of degradation compared with the optimal in-order packet delivery to the devices. It then addresses the minimum delivery delay problem using instantly decodable network coding (IDNC). In particular, the dual interface IDNC graph is constructed to represent all feasible coding opportunities and conflict-free transmissions. Subsequently, the minimum delivery delay problem is shown to be equivalent to a maximum weight independent set selection problem over the dual interface IDNC graph. Simulation results demonstrate that the proposed IDNC algorithm effectively reduces the delivery delay as compared with the existing network coding algorithms. Especially, for a layered video transmission, the proposed solution provides a sequential delivering of video layers to individual devices.

Investigating the multipath extension of the GRE in UDP technology

MPT is a novel multipath technology based on the GRE in UDP tunnel specification. In this paper, the conceptual architecture of MPT is disclosed. The designed structure of MPT includes several useful components: the possibility for external software modules to change the run-time parameters (by using the control interface), the choice between flow-based and packet based mappings of tunnel traffic to paths, as well as optional guarantee of in-order packet delivery to the application. The throughput aggregation performance of MPT is investigated in both laboratory and production network environment. The production network measurements proved that MPT is capable for super-aggregation (i.e. the aggregated throughput is higher than the algebraic sum of the throughput of the paths).

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

Routing algorithm design for on-chip networks (OCNs) has become increasingly challenging due to high levels of integration and complexity of modern systems-on-chip (SoCs). The inherent unreliability of components, embedded oversized IP blocks, and fine-grained voltage-frequency islands (VFIs) management among others, raise several challenges in OCNs: (a) network topologies become irregular or asymmetric making circular route dependencies that lead to deadlock hard to detect; and (b) routing algorithms that lack strong load-balancing properties often saturate prematurely. In order to address the aforementioned deadlock and load-balancing problems, we propose the traffic balancing oblivious routing (TBOR) algorithm. It is a two-phase routing algorithm consisting of: (1) construction of the weighted acyclic channel dependency graph (CDG) for the OCN to efficiently maximize available resource utilization; and (2) channel ordering across turn models to keep the underlying CDG cycle-free to guarantee deadlock-freedom using one or more turn-models. Channel bandwidth utilization and traffic balancing are achieved through static virtual channel allocation according to residual bandwidth of healthy links. In addition, we introduce in this work two schemes of different granularity of fault detection and analysis while guaranteeing in-order packet delivery by assigning a unique path to each flow. Extensive experiments demonstrate the proposed routing methodology outperforms previous algorithms.

A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies

Large cluster-based machines require efficient high-performance interconnection networks. Routing is a key design issue of interconnection networks. Adaptive routing usually outperforms deterministic routing at the expense of introducing out-of-order packet delivery. Many of the commodity interconnects for clusters are based on fat-trees. The adaptive routing algorithm commonly used in fat-trees is composed of a fully adaptive upward subpath, followed by a deterministic downward subpath. As the latter is determined by the former, choosing the most adequate upward path for each packet is critical in fat-trees to achieve a good performance. In this paper, we present a mechanism for selecting the upward path in fat-trees, which enables optimum use of the available network resources to achieve a high network throughput. The proposed path selection is destination based, which allows reducing the head-of-line blocking effect. Indeed, the proposed mechanism can be used either as a selection function (the provided path is used as the preferred one), or as a deterministic routing algorithm (the path is the only possible one). The results show that the resulting selection function outperforms any other known one. Moreover, the proposed deterministic routing algorithm can achieve a similar, or even higher, level of performance than adaptive routing, while providing in-order packet delivery and a simpler switch implementation.

The optimal joint sequence design in the feedback-based two-stage switch

The feedback-based two-stage switch is scalable as it is configured by a predetermined and periodic joint sequence of configurations (Hu and Yeung, 2010). Its major problem is that the average packet delay is high under light traffic load. In this paper, we improve the performance of feedback-based switch while still ensuring in-order packet delivery and close to 100% throughput. We first show that the different sequences of configurations may endow a feedback-based switch with different delay performance. We propose to devise a tailor-made sequence of configurations for the coming traffic pattern. Given any traffic matrix, the optimal joint sequences that do exist can produce the lowest average packet delay. Then finding the optimal joint sequences is formulated as an ILP (Integer Linear Programming) problem. The simulation results demonstrate that the optimal joint sequence can cut down the average packet delay up to 14% under a random uniform traffic model and even 45% under a hot-spot traffic model. Last but not least, we also design a fast suboptimal algorithm for the practical implementation.

Deterministic Routing with HoL-Blocking-Awareness for Direct Topologies

Routing is a key design factor to obtain the maximum performance out of interconnection networks. Depending on the number of routing options that packets may use, routing algorithms are classified into two categories. If the packet can only use a single predetermined path, routing is deterministic, whereas if several paths are available, it is adaptive. It is well-known that adaptive routing usually outperforms deterministic routing. However, adaptive routers are more complex and introduces out-of-order delivery of packets. In this paper, we take up the challenge of developing a deterministic routing algorithm for direct topologies that can obtain a similar performance than adaptive routing, while providing the inherent advantages of deterministic routing such as in-order delivery of packets and implementation simplicity. The proposed deterministic routing algorithm is aware of the HoL-blocking effect, and it is designed to reduce it, which, as known, it is a key contributor to degrade interconnection network performance.

Balancing Performance and Cost in CMP Interconnection Networks

This paper presents an innovative router design, called Rotary Router, which successfully addresses CMP cost/performance constraints. The router structure is based on two independent rings, which force packets to circulate either clockwise or counterclockwise, traveling through every port of the router. These two rings constitute a completely decentralized arbitration scheme that enables a simple, but efficient way to connect every input port to every output port. The proposed router is able to avoid network deadlock, livelock, and starvation without requiring data-path modifications. The organization of the router permits the inclusion of throughput enhancement techniques without significantly penalizing the implementation cost. In particular, the router performs adaptive routing, eliminates HOL blocking, and carries out implicit congestion control using simple arbitration and buffering strategies. Additionally, the proposal is capable of avoiding end-to-end deadlock at coherence protocol level with no physical or virtual resource replication, while guaranteeing in-order packet delivery. This facilitates router management and improves storage utilization. Using a comprehensive evaluation framework that includes full-system simulation and hardware description, the proposal is compared with two representative router counterparts. The results obtained demonstrate the Rotary Router's substantial performance and efficiency advantages.

Large Deviations for Re-Sequencing Buffer Size

In-order delivery of packets is a key issue in data communication networks. Re-sequencing delay and re-sequencing buffer size are two important measures in design, performance and optimization. In this paper, a large deviation result is proved for the re-sequencing buffer, which is fed by m parallel M/M/1 queues. The result provides a limit for the probability of a large buffer. This limit can be significantly simplified when the m parallel M/M/1 queues are symmetric; that is, with the same arrival and service rates, respectively. The large deviation result obtained in this paper extends a recent result in the literature.

Load-balanced three-stage switch

A load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at outputs. In a recent work, the packet mis-sequencing problem is elegantly solved by a feedback-based switch architecture. In this paper, we extend the feedback-based switch from two-stage to three-stage for further cutting down average packet delay while still ensuring in-order packet delivery and close to 100% throughput. The basic idea is to use the third stage switch to map heavy flows to experience less middle-stage delays. To identity heavy flows, an adaptive traffic estimation algorithm is proposed. To ensure max–min fairness in bandwidth allocation under any inadmissible traffic pattern, an efficient fair scheduler is devised.

OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees

High-speed interconnection networks are essential elements for different high-performance parallel-computing systems. One of the most common interconnection network topologies is the fat-tree, whose advantages have turned it into the favorite topology of many interconnect designers. One of these advantages is the possibility of using simple but efficient routing algorithms, like the recently proposed deterministic routing algorithm referred to as DET, which offers similar (or better) performance than Adaptive Routing while reducing complexity and guaranteeing in-order packet delivery. However, as other deterministic routing proposals, DET cannot react when packets intensely contend for network resources, leading to the appearance of Head-of-Line (HoL) blocking which spoils network performance. In this paper, we describe and evaluate a simple queue scheme that efficiently reduces HoL-blocking in fat-trees using the DET routing algorithm, without significantly increasing switch complexity and required silicon area. Additionally, we propose an implementation of OBQA in a feasible switch architecture.

Why Can Some Advanced Ethernet NICs Cause Packet Reordering?

Intel Ethernet Flow Director is an advanced network interface card (NIC) technology. It provides the benefits of parallel receive processing in multiprocessing environments and can automatically steer incoming network data to the same core on which its application process resides. However, our analysis and experiments show that Flow Director cannot guarantee in-order packet delivery in multiprocessing environments. Packet reordering causes various negative impacts. E.g., TCP performs poorly with severe packet reordering. In this paper, we use a simplified model to analyze why Flow Director can cause packet reordering. Our experiments verify our analysis.

Feedback-Based Scheduling for Load-Balanced Two-Stage Switches

A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unlike existing approaches, we show that the efforts made in load balancing and keeping packets in order can complement each other. Specifically, at each middle-stage port between the two switch fabrics of a load-balanced switch, only a single-packet buffer for each virtual output queueing (VOQ) is required. Although packets belonging to the same flow pass through different middle-stage VOQs, the delays they experience at different middle-stage ports will be identical. This is made possible by properly selecting and coordinating the two sequences of switch configurations to form a joint sequence with both <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">staggered symmetry property</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-order packet delivery property</i> . Based on the staggered symmetry property, an efficient feedback mechanism is designed to allow the right middle-stage port occupancy vector to be delivered to the right input port at the right time. As a result, the performance of load balancing as well as the switch throughput is significantly improved. We further extend this feedback mechanism to support the multicabinet implementation of a load-balanced switch, where the propagation delay between switch linecards and switch fabrics is nonnegligible. As compared to the existing load-balanced switch architectures and scheduling algorithms, our solutions impose a modest requirement on switch hardware, but consistently yield better delay-throughput performance. Last but not least, some extensions and refinements are made to address the scalability, implementation, and fairness issues of our solutions.

CR Switch: A Load-Balanced Switch With Contention and Reservation

Load-balanced switches have received a great deal of attention recently as they are much more scalable than other existing switch architectures in the literature. However, as there exist multiple paths for flows of packets to traverse through load-balanced switches, packets in such switches may be delivered out of order. In this paper, we propose a new switch architecture, called the contention and reservation (CR) switch, that not only delivers packets in order but also guarantees 100% throughput. The key idea, as in a multiple-access channel, is to operate the CR switch in two modes: 1) the contention mode in light traffic and 2) the reservation mode in heavy traffic. To do this, we invent a new buffer management scheme, called virtual output queue with insertion (I-VOQ).With the I-VOQ scheme, we give rigorous mathematical proofs for 100% throughput and in-order packet delivery of the CR switch. By computer simulations, we also demonstrate that the average packet delay of the CR switch is considerably lower than other schemes in the literature, including the uniform frame spreading scheme [10], the padded frame scheme [8], and the mailbox switch [5].

Using Parallel DRAM to Scale Router Buffers

This paper addresses the design of high-performance buffers for high-end Internet routers. The buffers are typically implemented using a combination of SRAM and DRAM technologies in order to simultaneously meet the routers' high speed and capacity requirements. The major challenge in designing router buffers is to maintain multiple flow queues in the memory, unlike computer memory buffers (i.e., memory system). The major objective is to minimize the use of expensive but fast SRAM while providing acceptable delay guarantees to packets. In this paper, we first investigate hybrid SRAM/DRAM solutions proposed in the past. We show that one of the architectural limitations of these solutions is that the required SRAM size grows linearly with the number of flows in the system. This prevents the solutions from scaling to support a large number of flows. We then break down this shortcoming by proposing a parallel hybrid SRAM/DRAM (PHSD) architecture. We design a series of memory management algorithms (MMAs) for PHSD, based on tradeoffs between the complexity of the MMAs and the guarantee of in-order delivery of packets (segmentations). We perform a detailed analysis of the proposed algorithms and conduct extensive simulations to show that PHSD can significantly outperform solutions proposed in the past in terms of the SRAM requirements and packet delay.

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today's NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.

Parallel Switch System with QoS Guarantee for Real-Time Traffic

This paper studies the load-balancing algorithm and quality of service (QoS) control mechanism in a 320Gb/s switch system, which incorporates four packet-level parallel switch planes. Eight priorities for both unicast and multicast traffic are implemented, and the highest priority with strict QoS guarantee is designed for real-time traffic. Through performance analysis under multi-priority burst traffic, we demonstrate that the load-balancing algorithm is efficient, and the switch system not only provides excellent performance to real-time traffic, but also efficiently allocates bandwidth among other traffic of lower priorities. As a result, this parallel switch system is more scalable towards next generation core routers with QoS guarantee, as well as ensures in-order delivery of IP packets.

Enforcing in-order packet delivery in system area networks with adaptive routing

Adaptive routing, which dynamically selects the route of packets, has been widely studied for interconnection networks in massively parallel computers and system area networks. Although adaptive routing has the advantage of providing high bandwidth, it may deliver packets out-of-order, which some message passing libraries do not accept. In this paper, we propose two mechanisms called (1) FIFO transmission and (2) couple limitation to guarantee in-order packet delivery in adaptive routing. Both of them limit packet injection at source hosts. The FIFO transmission completely avoids packet sorting at destination hosts, while the couple limitation uses a few buffers to sort packets at destination hosts. Evaluation results show that the FIFO transmission and the couple limitation achieve a similar throughput to that of a method equipped with huge (infinite) buffers enough to store all out-of-order packets at destination hosts under both synthetic traffic and NAS Parallel Benchmarks.