Data Memory Research Articles

Heracles

Performance-monitoring timeseries systems such as Prometheus and InfluxDB play a critical role in assuring reliability and operationally. These systems commonly adopt a column-oriented storage model, by which timeseries samples from different time-series are separated, and all samples (with both numeric values and timestamps) in one timeseries are grouped into chunks and stored together. As a group of timeseries are often collected from the same source with the same timestamps, managing timestamps and metrics in a group manner provides more opportunities for query and insertion optimization but posts new challenges as well. Besides, for performance monitoring systems, to support better compression and efficient queries for most recent data that are most likely accessed by users, huge volumes of data are first cached in memory and then periodically flushed to disks. Periodic data flushing incurs high IO overhead, and simply discarding flushed data, which can still serve queries, not only is a waste but also brings huge memory reclamation cost. In this paper, we propose Heracles which integrates two techniques - (1) a new storage model, which enables efficient queries on compressed data by utilizing the shared timestamp column to easily locate corresponding metric values; (2) a novel two-level epoch-based memory manager, which allows the system to gradually flush and reclaim in-memory data while unreclaimed data can still serve queries. Heracles is implemented as a standalone module that can be easily integrated into existing performance monitoring timeseries systems. We have implemented a fully functional prototype with Heracles based on Prometheus tsdb, a representative open-source performance monitoring system, and conducted extensive experiments with real and synthetic timeseries data. Experimental results show that, compared with Prometheus, Heracles can improve the insertion throughput by 171%, and reduce the query latency and space usage by 32% and 30%, respectively, on average. Besides, to compare with other state-of-the-art storage techniques, we have integrated LevelDB (for LSM-tree-based structure) and Parquet (for column stores) into Prometheus tsdb, respectively, and experimental results show Heracles outperform these two integrations. We have released the open-source code of Heracles for public access.

A new EM algorithm for flexibly tied GMMs with large number of components

Gaussian mixture models (GMMs) are a family of generative models used extensively in many machine learning applications. The modeling power of GMMs is directly linked to the number of components. Memory, computational load and lack of enough data hinders using GMMs with large number of components. To tackle this problem, GMMs with a tying scheme that we call flexibly tied GMM was proposed in the literature of the speech recognition community. In the literature, a coordinate-descent EM algorithm was proposed for estimating the parameters of flexibly tied GMMs.In this paper, we aim at reintroducing flexibly tied GMMs to the pattern recognition community. We rigorously investigate various optimization methods and see none of the out-of-the-box optimization methods can solve the parameter estimation problem due to the complexity of the cost function. To this end, we develop a fast Newton EM algorithm that combined with the coordinate descent EM algorithm, it significantly outperforms pure coordinate descent EM and all other optimization algorithms. Furthermore, we propose a computation factorization technique to increase the speed and decrease memory requirement of both Newton and coordinate descent EM algorithms in the case of large number of components. Experimental results on many datasets verifies the efficacy of the proposed algorithm. It also verifies that flexibly tied GMM outperforms both basic GMM and other types of tied GMMs on the datasets in terms of the log-likelihood. We also evaluate the performance of flexibly tied GMM on a clustering problem, and show that it can outperform basic GMM and kmeans algorithm.

Study on Effective Temporal Data Retrieval Leveraging Complex Indexed Architecture

Current intelligent information systems require complex database approaches managing and monitoring data in a spatio-temporal manner. Many times, the core of the temporal system element is created on the relational platform. In this paper, a summary of the temporal architectures with regards to the granularity level is proposed. Object, attribute, and synchronization group perspectives are discussed. An extension of the group temporal architecture shifting the processing in the spatio-temporal level synchronization is proposed. A data reflection model is proposed to cover the transaction integrity with reflection to the data model evolving over time. It is supervised by our own Extended Temporal Log Ahead Rule, evaluating not only collisions themselves, but the data model is reflected, as well. The main emphasis is on the data retrieval process and indexing with regards to the non-reliable data. Undefined value categorization supervised by the NULL_representation data dictionary object and memory pointer layer is provided. Therefore, undefined (NULL) values can be part of the index structure. The definition and selection of the technology of the master index is proposed and discussed. It allows the index to be used as a way to identify blocks with relevant data, which is of practical importance in temporal systems where data fragmentation often occurs. The last part deals with the syntax of the Select statement extension covering temporal environment with regards on the conventional syntax reflection. Event_definition, spatial_positions, model_reflection, consistency_model, epsilon_definition, monitored_data_set, type_of_granularity, and NULL_category clauses are introduced. Impact on the performance of the data manipulation operations is evaluated in the performance section highlighting temporal architectures, Insert, Update and Select statements forming core performance characteristics.

Downsampling-based synchrosqueezing transform and its applications on large-scale vibration data

Synchrosqueezing transform (SST) is a useful tool for vibration signal analysis due to its high time-frequency concentration and reconstruction properties. However, existing SST requires much processing time and memory for large-scale data. In this paper, some efficient implementation methods of SST based on downsampled short-time Fourier transform are proposed. By controlling the downsampling factor both in time and frequency, combined with the proposed selective reassignment and frequency subdivision scheme, one can keep a balance between efficiency and accuracy according to practical needs. Moreover, the reconstruction property is also available under the downsampling scheme. The effects of parameters on the concentration, computing efficiency, and reconstruction accuracy are also investigated quantitatively, followed by a mathematic model of reassignment behavior affected by decimating factors. Experimental results on an aero-engine and a spindle show that the downsampling-based SST can effectively characterize the non-stationary features of the large-scale vibration data to reveal the mechanism of mechanical systems.

Mille Cheval: a GPU-based in-memory high-performance computing framework for accelerated processing of big-data streams

Streams are temporally ordered, rapid changing, ample in volume, and infinite in nature. It is nearly impossible to store the entire data stream due to its large volume and high velocity. In this work, the principle of parallelism is employed to accelerate stream data computing. GPU-based high-performance computing (HPC) framework is proposed for accelerated processing of big-data streams using the in-memory data structure. We have implemented three parallel algorithms to prove the viability of the framework. The contributions of Mille Cheval are: (1) the viability of streaming on accelerators to increase throughput, (2) carefully chosen hash algorithms to achieve low collision rate and high randomness, and (3) memory sketches for approximation. The objective is to leverage the power of a single node using in-memory computing and hybrid computing. HPC does not always require high-end hardware but well-designed algorithms. Achievements of Mille Cheval are: (1) relative error is 1.32 when error rate and overestimate rate are chosen as 0.001 and (2) the host memory space requirement is just 63 MB for 1 terabyte of data. The proposed algorithms are pragmatic. It is evident from experimental results that the framework demonstrates 10X speed-up as compared with CPU implementations and 3X speed-up as compared with GPU implementations.

РЕГУЛЯРНА ОБЧИСЛЮВАЛЬНА СТРУКТУРА ДЛЯ РАНЖУВАННЯ ДАНИХ

The article discusses the functionality of a processor with a regular structure, the structural diagram is showed. Processor contains register memory, data memory, rank memory, an array of mask elements, a control unit, and an array of indicators. The data memory contains an array of input counters, and the rank memory contains an array of output counters. The processor not only performs sorting, but also has the ability to visualize the results of ranking sorted elements of the input array of numbers due to the display block, which contains rank memory and an array of indicators. The regularity of the processor structure is realized in the horizontal and vertical directions. This will make it possible to effectively place it in an FPGA chip with the possibility of modular expansion. The features of the functioning of the processor for sorting with ranking are analyzed, which makes it possible to speed up the processing process by using high-speed decrement/increment operations. These operations are applied according to an array of numbers and an array of ranks. The features of the sorting process in the processor are described and a block diagram of the algorithm is presented. The processor implements an alternative approach to vertical data processing, namely, parallel-vertical sorting of an array of numbers. The functional diagram of the mask element, an array of which plays the main role in the formation of the ranks of the sorted elements of a numeric array, is considered. The diagram of the connections of the chip of the initial counter and the seven-segment indicator, which are the components of the display block of the processor, is presented.

Аналитика в реальном времени, гибридная транзакционная/аналитическая обработка, управление данными в основной памяти и энергонезависимая память

These days, real-time analytics is one of the most often used notions in the world of databases. Broadly, this term means very fast analytics over very fresh data. Usually the term comes together with other popular terms, hybrid transactional/analytical processing (HTAP) and in-memory data processing. The reason is that the simplest way to provide fresh operational data for analysis is to combine in one system both transactional and analytical processing. The most effective way to provide fast transactional and analytical processing is to store an entire database in memory. So on the one hand, these three terms are related but on the other hand, each of them has its own right to life. In this paper, we provide an overview of several in-memory data management systems that are not HTAP systems. Some of them are purely transactional, some are purely analytical, and some support real-time analytics. Then we overview nine in-memory HTAP DBMSs, some of which don't support real-time analytics. Existing real-time in-memory HTAP DBMSs have very diverse and interesting architectures although they use a number of common approaches: multiversion concurrency control, multicore parallelization, advanced query optimization, just in time compilation, etc. Additionally, we are interested whether these systems use non-volatile memory, and, if yes, in what manner. We conclude that an emergence of new generation of NVM will greatly stimulate its use in in-memory HTAP systems.

High-Performance Predictable NVM-Based Instruction Memory for Real-Time Embedded Systems

Worst case execution time and energy consumption are two of the most important design constraints of real-time embedded systems and memory subsystem has a major impact on both of them. Therefore, many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories instead of conventional memories such as SRAM and DRAM. Indeed, the low leakage power dissipation and improved density of emerging non-volatile memories make them prime candidates for replacing the conventional memories. However, accessing these memories imposes performance and energy overhead and using them as the instruction memory could increase the worst case execution time, which would have a negative impact on the system. Furthermore, most previous studies that have tried to address such problems have focused on the data memory and therefore their solutions are not suitable for the instruction memory. In this paper, a new instruction memory architecture for non-volatile memories is proposed which reduces the effective memory access latency by employing memory access interleaving technique. Unlike common instruction access latency improvement techniques such as prefetching which usually increase the worst case execution time of the system, the proposed architecture is predictable and does not increase the worst case execution time of the system. Furthermore, it improves both average case execution time and energy consumption of the system and requires no changes to the application code. The proposed architecture has been evaluated using different applications from MiBench and Malardalen benchmark suites and the results show that compared to previous studies, the proposed architecture can improve the memory energy consumption, the average case execution time, and the worst case execution time of the system by 73, 61, and 27 percent respectively.

Wireless Sensor Network Deployment in Cyberphysical Machine Tool System Based on Optimal Allocation of Memory Buffers

As an important direction of Industry 4.0, cyberphysical machine tool systems (CPMTS) can realize the deep integration and real‐time interaction of physical components and information to optimize manufacturing processes. Wireless sensor network (WSN), an important part of CPMTS, is responsible for data collection and transmission. However, in the process of data transmission, due to memory limitations and noise interference, unreasonable sensor distribution will affect the performance of CPMTS. At the same time, data accuracy will be affected due to the resource constraints of CPMTS. To solve the problems above, this paper firstly presented a single‐station transfer model to ensure the layout of sensors in each sink, which can meet the detection capability of fault/monitoring data. Then, by using fuzzy graphs, a multihop‐station transfer model and data‐collecting model are developed to describe the data flow and memory allocation in the wireless network. Taking noise interference and data position into consideration, a MILP problem is formulated and the optimization solution is obtained by using the “branch and bound” method. Finally, case studies about optimal sensor distribution on the single station and path optimization on the multihop station are presented to illustrate the proposed strategy. The case studies validated that the proposed sensor distribution in a single station can achieve higher detectability with fewer resources, and the optimization path strategy can achieve the best performance in two proposed experiments, compared to the shortest path and noninferior path strategies.

A Study on Modeling and Optimization of Memory Systems

Accesses Per Cycle (APC), Concurrent Average Memory Access Time (C-AMAT), and Layered Performance Matching (LPM) are three memory performance models that consider both data locality and memory assess concurrency. The APC model measures the throughput of a memory architecture and therefore reflects the quality of service (QoS) of a memory system. The C-AMAT model provides a recursive expression for the memory access delay and therefore can be used for identifying the potential bottlenecks in a memory hierarchy. The LPM method transforms a global memory system optimization into localized optimizations at each memory layer by matching the data access demands of the applications with the underlying memory system design. These three models have been proposed separately through prior efforts. This paper reexamines the three models under one coherent mathematical framework. More specifically, we present a new memory- centric view of data accesses. We divide the memory cycles at each memory layer into four distinct categories and use them to recursively define the memory access latency and concurrency along the memory hierarchy. This new perspective offers new insights with a clear formulation of the memory performance considering both locality and concurrency. Consequently, the performance model can be easily understood and applied in engineering practices. As such, the memory-centric approach helps establish a unified mathematical foundation for model-driven performance analysis and optimization of contemporary and future memory systems.

A GPU-Accelerated In-Memory Metadata Management Scheme for Large-Scale Parallel File Systems

Driven by the increasing requirements of high-performance computing applications, supercomputers are prone to containing more and more computing nodes. Applications running on such a large-scale computing system are likely to spawn millions of parallel processes, which usually generate a burst of I/O requests, introducing a great challenge into the metadata management of underlying parallel file systems. The traditional method used to overcome such a challenge is adopting multiple metadata servers in the scale-out manner, which will inevitably confront with serious network and consistence problems. This work instead pursues to enhance the metadata performance in the scale-up manner. Specifically, we propose to improve the performance of each individual metadata server by employing GPU to handle metadata requests in parallel. Our proposal designs a novel metadata server architecture, which employs CPU to interact with file system clients, while offloading the computing tasks about metadata into GPU. To take full advantages of the parallelism existing in GPU, we redesign the in-memory data structure for the name space of file systems. The new data structure can perfectly fit to the memory architecture of GPU, and thus helps to exploit the large number of parallel threads within GPU to serve the bursty metadata requests concurrently. We implement a prototype based on BeeGFS and conduct extensive experiments to evaluate our proposal, and the experimental results demonstrate that our GPU-based solution outperforms the CPU-based scheme by more than 50% under typical metadata operations. The superiority is strengthened further on high concurrent scenarios, e.g., the high-performance computing systems supporting millions of parallel threads.

HADOOP: A Comparative Study between Single-Node and Multi-Node Cluster

Data analysis has become a challenge in recent years as the volume of data generated has become difficult to manage, therefore more hardware and software resources are needed to store and process this huge amount of data. Apache Hadoop is a free framework, widely used thanks to the Hadoop Distributed Files System (HDFS) and its ability to relate to other data processing and analysis components such as MapReduce for processing data, Spark - in-memory Data Processing, Apache Drill - SQL on Hadoop, and many other. In this paper, we analyze the Hadoop framework implementation making a comparative study between Single-node and Multi-node cluster on Hadoop. We will explain in detail the two layers at the base of the Hadoop architecture: HDFS Layer with its deamons NameNode, Secondary NameNode, DataNodes and MapReuce Layer with JobTrackers, TaskTrackers daemons. This work is part of a complex one aiming to perform data processing in Data Lake structures.

Wave equation for underground viscoelastic media and wavefield numerical simulation

The energy of wavefield is gradually attenuated in all real materials, which is a fundamental feature and more obvious in the media containing liquid and gas. Because the viscosity effect is not considered in the classical wave theory, the actual wavefield is different from the simulated scenario based on the assumption of complete elasticity so that the application of wavefield does not meet the expectations in engineering technology, such as geophysical exploration. In the rock physics field, the well-known constant-<i>Q</i> theory gives a linear description of attenuation and <i>Q</i> is regarded as independent of the frequency. The quality factor <i>Q</i> is a parameter for calculating the phase difference between stress and strain of the media, which, as an index of wavefield attenuation behavior, is inversely proportional to the viscosity. Based on the constant-<i>Q</i> theory, a wave equation can be directly obtained by the Fourier transform of the dispersion relation, in which there is a fractional time differential operator. Therefore, it is difficult to perform the numerical simulation due to memory for all historical wavefields. In this paper, the dispersion relation is approximated by polynomial fitting and Taylor expansion method to eliminate the fractional power of frequency which is uncomfortably treated in the time domain. And then a complex-valued wave equation is derived to characterize the propagation law of wavefield in earth media. Besides the superiority of numerical simulation, the other advantage of this wave equation is that the dispersion and dissipation effects are decoupled. Next, a feasible numerical simulation strategy is proposed. The temporal derivative is solved by the finite-difference approach, moreover, the fractional spatial derivative is calculated in the spatial frequency domain by using the pseudo-spectral method. In the process of numerical simulation, only two-time slices, instead of the full-time wavefields, need to be saved, so the demand for data memory significantly slows down compared with solving the operator of the fractional time differential. Following that, the numerical examples prove that the novel wave equation is capable and efficient for the homogeneous model. The research work contributes to the understanding of complex wavefield phenomena and provides a basis for treating the seismology problems.

IMPROVEMENT OF ICS OF POWER PLANT UNIT FOR DIFFERENT MODES OF OPERATION

The analysis of the criteria for improving the technical and economic efficiency in the operation of the electric power equipment of power units of power plants. It is indicated that the existing methods for calculating the technical and economic effect do not take into account the factors that lead to technical and economic costs when the power unit is stopped and the load of electricity consumers is reduced. A significant factor in increasing the technical and economic efficiency in the operation of automated control systems for technological processes at the power unit of the power plant is operational control to identify information with a low level of reliability. It is shown that the reliability of the functioning of the technological equipment of the power unit significantly depends on the efficiency of automated control in emergency situations, when unauthorized shutdowns of the power unit occur due to false alarms. It was found that the reason for false alarms is information about the parameters of the technological process of the power unit, which is characterized by a low degree of reliability. It is shown that unforeseen unauthorized shutdowns of the power unit and a decrease in the load for power consumers lead to significant economic and material losses, and, consequently, to a decrease in technical and economic efficiency with automated control of the power unit. It is shown that the applied technical and economic models do not take into account financial and material costs that occur due to an unauthorized shutdown of the power unit and a decrease in the load for electrical consumers in case of false alarms in real time. A unified integrated economic and mathematical model has been developed, which allows calculating the economic effect, taking into account the change in the reliability of the technological equipment of the power unit, due to the timely prompt detection of false alarms and information with a low degree of reliability. To calculate the economic effect on the basis of the developed unified economic and mathematical model, a modular block of the mode of emergency situations is proposed, associated with the modules of false positives and emergency signs, taking into account the static and operational technical and economic components. Practical recommendations are given for using the technical and economic module in the software and hardware complex of the power unit, which allows calculating the technical and economic effect based on statistical data coming from the data memory and current data from the power unit.

ТЕМПЕРАТУРНИЙ КОНТРОЛЕР НА СУЧАСНИХ НАПІВПРОВІДНИКОВИХ ДАТЧИКАХ

The ultra-fast development of electronics in the last decade, as well as the constant reduction in the price of electronic components, lead to the fact that many manufacturers of household and industrial equipment replace electromechanical components with microcontroller-controlled electronic circuits in the manufactured equipment. The regulator, on the bimetallic plate and the mechanical timer are inferior in many respects to the electronic regulator and the digital timer. In this work, there was a study of an intelligent temperature module, since in industrial automation there is a tendency for widespread use of such intelligent sensor devices and microcontrollers that collect information, preprocess it, and then forward or store it. Such modules can work autonomously, collecting information about the measurement object and accumulating it until the moment of transfer to the operator (usually implemented on the basis of battery power), or they can be combined into a sensor network while standing but interacting with the main measurement unit. The sensor is powered via an interface cable, and in some cases using signal lines. The criteria for choosing a microcontroller for these purposes are: 1. Kernel performance, the required size of program and data memory, a sufficient number of I / O port lines. 2. The cost of the microcontroller. 3. Technical parameters of the microcontroller (supply voltage range, operating temperature range, resistance to electromagnetic interference). 4. The life cycle of the selected family. 5. FLASH-memory of programs possessing a sufficient resource for programming (minimum resource 1000 times, desirable 100 000). 6. Reduction to the actually necessary value of the frequency of the processor (the use of clock quartz in order to reduce current consumption). 7. Power supply to peripheral microcircuits (external ADCs, FLASH-memory) directly from the processor outputs or through key elements only for the duration of their operation. In the article, a circuit diagram based on the PIC16F84A microcontroller is designed, in which a general circuit model based on Brock’s cell and an operational amplifier-comparator was used as a heat-sensitive sensor. A feature of this microcontroller system is that it is equipped with an optocoupler and triac assembly, which allows you to connect a powerful load of up to 20 A and control it remotely. In addition, volt-temperature characteristics for the presence of non-linearity were considered in the work and the choice of sensor was justified. Keywords: microcontroller, data acquisition system, temperature, measurement error.

SMConf: One-Size-Fit-Bunch, Automated Memory Capacity Configuration for In-memory Data Analytic Platform

Spark is the most popular in-memory processing framework for big data analytics. Memory is the crucial resource for workloads to achieve performance acceleration on Spark. The extant memory capacity configuration approach in ... | Find, read and cite all the research you need on Tech Science Press

Exploiting Sharing Join Opportunities in Big Data Multiquery Optimization with Flink

Multiway join queries incur high-cost I/Os operations over large-scale data. Exploiting sharing join opportunities among multiple multiway joins could be beneficial to reduce query execution time and shuffled intermediate data. Although multiway join optimization has been carried out in MapReduce, different design principles (i.e., in-memory Big Data platforms, Flink) are not considered. To bridge the gap of not considering the optimization of Big Data platforms, an end-to-end multiway join over Flink, which is called Join-MOTH system (J-MOTH), is proposed to exploit sharing data granularity, sharing join granularity, and sharing implicit sorts within multiple join queries. For sharing data, our previous work, Multiquery Optimization using Tuple Size and Histogram (MOTH) system, has been introduced to consider the granularity of sharing data opportunities among multiple queries. For sharing sort, our previous work, Sort-Based Optimizer for Big Data Multiquery (SOOM), has been introduced to consider the implicit sorts among join queries. For sharing join, additional modules have been tailored to the J-MOTH optimizer to optimize sharing work by exploiting shared pipelined multiway join among multiple multiway join queries. The experimental evaluation has demonstrated that the J-MOTH system outperforms the naive and the state-of-the-art techniques by 44% for query execution time using TPC-H queries. Also, the proposed J-MOTH system introduces maximal intermediate data size reduction by 30% in average over Hadoop-like infrastructures.

RETRACTED: Big Data Development of Tourism Resources Based on 5G Network and Internet of Things System

With the improvement of information development level, the development speed of big data is also very fast, more and more fields are using big data to manage. Different departments and enterprises get more information from data, and big data is used more and more frequently. However, it is more and more contradictory to the demand for big data that the traditional data technology platform and system can not meet the increasing demand of big data. These traditional data systems and data platforms usually have the disadvantages of slow response, small data memory and certain uncertainty of recorded content. Therefore, big data is developed and studied to increase the volume and accuracy of data systems and platforms. This paper studies the development and utilization of big data by analyzing neural network. The main purpose is to make the big data system and platform more perfect. Some technical requirements and program requirements in big data also gradually adapt to the consistency of data platform and data system. The improvement of people's living standard also promotes the rapid development of tourism. The inclusion of tourism in the Internet of things has become a new technological requirement. Intelligent tourism has been recognized and used by more and more people. Because the Internet of things has a very powerful amount of information, more and more people, especially young people, prefer to travel intelligently through the Internet of things. This paper points out that tourists choose to use machine classification through the Internet of things. This classification can help tourists make better choices. The accuracy of this method is verified by experiments.

Traffic-Aware Erasure-Coded Archival Schemes for In-Memory Stores

Redundancy schemes are introduced to in-memory stores to provide fault tolerance. To achieve good trade-off between access performance and memory efficiency, it is appropriate to adopt replication and erasure coding to keep popular and unpopular data, respectively. Within such a hybrid-redundancy in-memory store, an issue of redundancy transition from replication to erasure coding (a.k.a., erasure-coded archival) should be addressed for unpopular in-memory datasets, since caching workloads exhibit long-tail distributions and most in-memory data are unpopular. If data replicas are distributed across nodes in randomly-selected racks, then subsequent data-block-replica retrieval for erasure-coded archival will create cross-rack traffic, and final parity-block relocation will cause extra cross-rack communications. In this article, we propose an encoding-oriented replica placement policy - ERP - by incorporating an interleaved declustering mechanism. We design two traffic-aware erasure-coded archival schemes -TEA-TL and TEA-SL - for ERP-powered in-memory stores by taking into account temporal locality and spatial locality, respectively. With ERP in place, both TEA-TL and TEA-SL schemes embrace the following three salient features: (i) they alleviate cross-rack traffic raised by retrieving required data-block replicas; (ii) they improve rack-level load balancing by distributing replicas via load-aware primary-rack-selection approach; and (iii) they mitigate block-relocation operations launched to sustain rack-level and node-level fault-tolerance. We conduct quantitative performance evaluations using the YCSB benchmark. The empirical results show that both TEA-TL and TEA-SL schemes not only bring forth lower cross-rack traffic than the four candidate encoding schemes, but also exhibit superb archival-throughput and rack-level-balancing performance. In particular, within a group of comparative tests using the baseline configurations, TEA-TL and TEA-SL accelerate archival throughput by at least 36.3 and 70.8 percent, respectively; both TEA-TL and TEA-SL schemes improve rack-level load-balancing by a factor of more than 1.45x relative to the four candidate encoding schemes.

RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining

RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. The processor applies three effective optimization methods to improve the operating frequency. These methods are instruction fetch unit optimization including pipelined branch prediction mechanism, ALU optimization, and data alignment and sign-extension optimization for data memory output. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.