РЕГУЛЯРНА ОБЧИСЛЮВАЛЬНА СТРУКТУРА ДЛЯ РАНЖУВАННЯ ДАНИХ

Abstract

The article discusses the functionality of a processor with a regular structure, the structural diagram is showed. Processor contains register memory, data memory, rank memory, an array of mask elements, a control unit, and an array of indicators. The data memory contains an array of input counters, and the rank memory contains an array of output counters. The processor not only performs sorting, but also has the ability to visualize the results of ranking sorted elements of the input array of numbers due to the display block, which contains rank memory and an array of indicators. The regularity of the processor structure is realized in the horizontal and vertical directions. This will make it possible to effectively place it in an FPGA chip with the possibility of modular expansion. The features of the functioning of the processor for sorting with ranking are analyzed, which makes it possible to speed up the processing process by using high-speed decrement/increment operations. These operations are applied according to an array of numbers and an array of ranks. The features of the sorting process in the processor are described and a block diagram of the algorithm is presented. The processor implements an alternative approach to vertical data processing, namely, parallel-vertical sorting of an array of numbers. The functional diagram of the mask element, an array of which plays the main role in the formation of the ranks of the sorted elements of a numeric array, is considered. The diagram of the connections of the chip of the initial counter and the seven-segment indicator, which are the components of the display block of the processor, is presented.