We use semiconductor Integrated Circuit (IC) chips in our day-to-day life. ICs are placed in electronic devices that have become integral part of human life. With the advancement in human's modus vivendi, there comes a requirement of fast-growing technology which can only be achieved by narrowing the gap between design and manufacturing communities. As the semiconductor industry has matured over the year with reduced technology nodes, with 3D (3-Dimensional) structures, there has been a constant emphasis on yield, quality and reliability of the ICs. The technology and process complexity of today's ICs demand testing to monitor yield, performance, and reliability be performed during the manufacturing process. Chipmakers are using various tools to avoid losses with respect to quality and cost of the chip. With great challenge to find defects on lower technology node, comes the need for more accurate and efficient way of inspection. Failure Analysis (FA) results in the conventional process are no longer relevant to designs on new technology nodes. The proposed method in the paper, the FA results are fed back to upstream manufacturing process for corrective action. In this environment, traditional FA activities are finding an expanded role: Predictive FA. Proposed paper is an effort to overcome the traditional FA scenario using Predictive FA. A subset of artificial intelligence (AI), machine learning (ML) comes in rescue for the same. Integrating the algorithms of ML with image processing and pattern search to find the unique patterns of defects by making the machine to build a library (training data) of all the defects observed during FA and use the learning on test data. It will generate ability to predict new defects after being trained with enough scenarios. One such learning type is reinforcement learning, the machine is exposed to an environment where it trains itself continually. It learns from experience and try to make accurate decisions. This learning loop from FA to the inline inspection tools aids to better analysis of defects at a prior stage and detect potential failures in chip.