In-band Noise Floor Research Articles

A 0.1-1.9GHz 65nm CMOS variable-gain mixer-first receiver with DSA and noise-shaping TIA

In this letter, we proposed a highly linear mixer-first receiver with a discrete-step attenuator (DSA) and a noise-shaping TIA. A resistor-reuse technique is devoted to improving linearity and attenuation flatness of the DSA with frequency independance, and a negative impedance chopping method is proposed to reduce the in-band noise of the TIA. Measurement results show that the receiver achieves > 13 dBm IIP3 and in-band noise floor has been depressed by 4 dB, with only consuming 2.82 mW under 1.3 V supply.

A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <−67-dBc IM3 Within DC to 6-GHz Tunable Passbands

This paper presents a hybrid digital-to-analog converter (DAC) architecture with a tunable bandpass delta-sigma modulator (DSM) to synthesize channelized signals over a wide frequency range with high linearity and a low in-band noise floor. Due to the mostly digital architecture, this DAC topology favors technology scaling. The DSM uses a successive pipeline structure with time-interleaving techniques to achieve a 12-GS/s data rate and overall 16-bit DAC resolution. To improve the linearity at high frequencies, an inverse-sinc-shaped digital pre-distortion (DPD) scheme is used to better approximate and compensate the timing errors. The DAC can be configured for single- or dual-rate operation modes to tradeoff different input data rates with DAC linearity and spectral images. The prototype was fabricated in 65-nm CMOS technology with an analog area of 0.1 mm2 and 60 dBc up to a 4.2-GHz signal frequency at 12 GS/s in the single-rate mode thanks to the hybrid structure and proposed DPD techniques.

A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <−80 dBc IM3 up to 1 GHz in 65 nm CMOS

This paper presents a 12-bit 2 GS/s dual-rate hybrid DAC using bandwidth- and linearity-enhancement techniques. The proposed pulsed-error pre-distortion scheme enhances DAC linearity at both low and high signal frequencies by leveraging the fine time-and-voltage resolution from the oversampling path of the hybrid DAC structure. To further widen the DAC bandwidth, a noise-cancellation scheme is proposed to suppress the quantization noise of the delta-sigma modulator within DC to the 1 GHz band without increasing modulator complexity. The analytical derivations and numerical simulations of the proposed techniques are provided to demonstrate the technique’s effectiveness, as well as its practical design constraints. A proof-of-concept silicon prototype is implemented in 65 nm standard CMOS that achieves SFDR of 74–98 dBc over the DC-1GHz Nyquist band. In a two-tone measurement, the IM3 product is measured from 101 dBc to 80 dBc across the Nyquist band. The SFDR improvement after enabling the proposed pulsed pre-distortion scheme measures from 67.5 to 74.4dBc, while the in-band noise floor demonstrates 6 dB suppression at the Nyquist band edge after enabling the noise-cancellation scheme.

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and $\Delta \Sigma $ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of $-$ 104 dBc/Hz and 1.5 ps $_{\rm rms}$ integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of $-$ 225.8 dB.

A 2.8–3.2-GHz Fractional-$N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO

A 2.8–3.2-GHz fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex> </formula> digital PLL, implemented in 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu \hbox{m}$</tex></formula> CMOS, is presented. The PLL architecture has the form of a classic delta-sigma fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex></formula> PLL. A PFD generates up and down pulses from the reference and divided-down digitally controlled oscillator (DCO) clock. The time-to-digital converter (TDC) converts the width of up pulses to digital words. The quantization noise introduced by a third-order delta-sigma modulator through the multi-modulus divider is canceled at the TDC output. A resistively interpolated ADC is employed to boost TDC resolution by a factor of five. A dither-less DCO with an inductively coupled fine-tuned varactor bank improves tuning step-size by a factor of 16.6, to 20 kHz. With a 52-MHz reference clock, a 3.2-GHz output clock, and a loop-bandwidth of 950 kHz, this prototype achieves 230-fs rms jitter, integrated from a 1-kHz to 40-MHz offset, while drawing 17 mW from a 1.8-V supply. The in-band phase noise floor is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{111.6 dBc/Hz}$</tex></formula> at a 500-kHz offset. The reference spur is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{75 dBc}$</tex></formula> and the worst-case fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$N$</tex> </formula> spur, by sweeping the multiplication ratio near 61, is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{55 dBc}$</tex></formula> . An FOM of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-\hbox{240.4 dB}$</tex></formula> is achieved, and this design occupies a core area of 0.62 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{mm}^{2}$</tex> </formula> .

A Qualification Approach to DAC Mismatch-Shaping Methods

Linearizing a digital-to-analog converter by mismatch noise shaping is popular particularly in the art of Delta-Sigma converters. This work proposes a procedure for characterizing and benchmarking the shaping methods. The proposed approach provides five graphical figures of merit related to in-band spurious level and noise floor. In our case-studies, we will concentrate on the data-weighted averaging method with low- and bandpass shaping alongside a combination of two-tone suppression methods.

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them inferior to traditional analog solutions. The investigation in this paper shows that in-band output spurs, the major shortcoming of wideband divider-less ADPLLs with respect to analog fractional PLLs, are intrinsic and due to the finite resolution of the time-to-digital converter (TDC), even assuming perfect quantization and linearity. Moreover, even if the conceptual spur level is arbitrarily reduced by increasing the TDC resolution, TDC nonlinearities can cause a significant spur re-growth. This paper proposes two techniques to reduce the gap between all-digital and analog implementations of wideband fractional PLLs. These techniques have been applied to a 3 GHz ADPLL, whose bandwidth is programmable from 300 kHz to 1.8 MHz, operating from a 25 MHz reference signal. The test chip features more than 10 dB of worst in-band spur reduction when both corrections are active, for a worst-case in-band spur of -45 dBc at a bandwidth of 1.8 MHz and an in-band noise floor of -101 dBc/Hz. The chip core occupies 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65 nm CMOS technology, and consumes less than 10 mW from a 1.2 V supply.

Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta–Sigma Modulators

We analyze the effect of nonlinearity in the first integrator of a single-loop multibit continuous-time delta-sigma modulator, when the loop filter is of the cascade of integrators with feedforward kind. When a multibit quantizer is used in the loop, we show that integrator nonlinearity results in an increased in-band noise (IBN) floor. We develop analytical relations for the IBN spectral density for several opamp topologies, assuming that the shaped quantization noise is approximately Gaussian. Our results agree well with macromodel and transistor level simulations.

A First-Order Tree-Structured DAC With Reduced Signal-Band Noise

A mismatch-shaping tree-structured digital-to-analog converter (DAC) utilizes several layers of switching blocks to spectrally shape the DAC circuit errors. A first-order mismatch-shaping DAC using un-dithered switching sequences for the switching blocks results in spurious tones in the DAC noise. The unwanted tones can be eliminated from the DAC noise by employing white dither sequences to randomly select two types of short root symbols to be placed in the switching sequences. Dithered switching sequences, unfortunately, result in a higher noise floor in the DAC noise, in comparison with un-dithered switching sequences. In this brief, we propose an improved first-order sequencing logic to eliminate unwanted tones while causing only a modest increase in the in-band noise floor at a very modest hardware cost. Our mismatch-shaping sequencing logic is based on the scheme using a white dither sequence to randomly select each symbol between two specific types of long root symbols. Alternatively, our scheme can be viewed as using a high-pass dither sequence to randomly select the short root symbols. An analytical formula for the power-spectral density of the proposed switching sequence is presented to show its improvement over the prior first-order switching sequence. It is also shown from numerical simulations that the proposed switching sequence improves the signal-to-noise plus distortion ratio by more than 5 dB for a sigma-delta modulator with static DAC-element errors chosen from a Gaussian distribution with a standard deviation of 1%

A Wideband 2.4-GHz Delta-Sigma Fractional-&amp;gt;tex&amp;lt;$N$&amp;gt;/tex&amp;lt;PLL With 1-Mb/s In-Loop Modulation

A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.

Techniques for in-band phase noise reduction in ΔΣ synthesizers

This paper reviews several techniques used to reduce the in-band phase noise contribution of /spl Delta//spl Sigma/ fractional-N frequency synthesizers. The paper develops several practical techniques for specifying the noise and linearity of components used in a /spl Delta//spl Sigma/ fractional-N synthesizer. As an example, it presents a synthesizer with an in-band phase noise floor of -97 dBc/Hz@10 KHz for an RF output frequency of 2.432 GHz and a reference frequency of 16 MHz. The synthesizer has a frequency resolution of 61 Hz and an on-chip crystal oscillator. The synthesizer was implemented in a 0.35-/spl mu/m SiGe process and consumes 6 mA from a 3 V supply. The in-band phase-noise, spurs, and power consumption of this synthesizer are each low and comparable to the state of the art.