A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Abstract

Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them inferior to traditional analog solutions. The investigation in this paper shows that in-band output spurs, the major shortcoming of wideband divider-less ADPLLs with respect to analog fractional PLLs, are intrinsic and due to the finite resolution of the time-to-digital converter (TDC), even assuming perfect quantization and linearity. Moreover, even if the conceptual spur level is arbitrarily reduced by increasing the TDC resolution, TDC nonlinearities can cause a significant spur re-growth. This paper proposes two techniques to reduce the gap between all-digital and analog implementations of wideband fractional PLLs. These techniques have been applied to a 3 GHz ADPLL, whose bandwidth is programmable from 300 kHz to 1.8 MHz, operating from a 25 MHz reference signal. The test chip features more than 10 dB of worst in-band spur reduction when both corrections are active, for a worst-case in-band spur of -45 dBc at a bandwidth of 1.8 MHz and an in-band noise floor of -101 dBc/Hz. The chip core occupies 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65 nm CMOS technology, and consumes less than 10 mW from a 1.2 V supply.