In-band IIP3 Research Articles

Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver Front-End for 5G Applications

A blocker-tolerant harmonic selection receiver front-end with RF bandwidth of 6.5 GHz to support the fifth-generation (5G) sub-6 GHz band is presented. The proposed N-path switching filter-based receiver employs harmonic recombination blocks at the baseband (BB) to select the desired local oscillator (LO) harmonics and suppress blockers. It is demonstrated how the configuration of two feed-forward N-path switching filters and BB harmonic recombination stage can be reconfigured to select the first harmonic of the switching frequency at the low-frequency band (0.5–1.9 GHz) and the third LO harmonic at the high-frequency band (1.95–6 GHz). Thus, the proposed architecture has the capability of supporting an RF input frequency of up to 6 GHz while the switching frequency operates up to 2 GHz. Higher harmonic selection in addition to the fundamental helps to reduce the power consumption and required input frequency of the multiphase LO clock generator. An RF receiver prototype is fabricated in a TSMC 130-nm CMOS technology. It achieves a 5 dB noise figure (NF), −16.6 dBm in-band input-referred third-order intercept point (IIP3), and 9 dBm out-of-band (OOB) IIP3, respectively, at the low-frequency band (0.5–1.9 GHz). The 2nd–5th harmonic rejection ratios (HRRs) are higher than 44 dB without any calibration. The receiver can tolerate a 0 dBm blocker at a 180 MHz offset from a 1 GHz switching frequency with an NF of 9.4 dB. Over the high-frequency band (1.95–6 GHz), the receiver’s NF is less than 7.1 dB. Moreover, in-band IIP3, OOB IIP3, and first HRR are higher than −21 dBm, 7 dBm, and 39 dB, respectively. The receiver achieves an S11 better than −10 dB over 0.5–6 GHz, and has a total power consumption of 17–22.5 mW from a 1.2 V supply.

A Reconfigurable Balun-LNA and Tunable Filter With Frequency-Optimized Harmonic Rejection for Sub-GHz and 2.4 GHz IoT Receivers

A CMOS reconfigurable balun-LNA and tunable filter is proposed for sub-GHz and 2.4 GHz IoT applications. The core of the LNA gain stage is composed of two cascaded inverters for the single-to-differential conversion, and the additional inverter is placed in the feedback path for the implementation of the active feedback. In the sub-GHz band, it operates as an active feedback LNA by enabling all inverter stages. At the narrow 2.4 GHz band, it operates as an inductive source degenerated LNA (ISDLNA) with a minimum noise figure (NF) by disabling the inverter in the feedback path. In order to suppress the unwanted local oscillator (LO) harmonic mixing in the sub-GHz band and provide the frequency-optimized harmonic rejection ratio (HRR), a reconfigurable Sallen-Key (SK) filter-based <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4^{\mathbf {th}}$ </tex-math></inline-formula> -order tunable filter is proposed on the basis of the modified super source follower (SSF) with enhanced loop gain. It covers the entire VHF band with a smaller capacitance tuning ratio by switching the polarity of the output of the modified SSF. Compared to previous works, this work provides the largest tuning range from 50 MHz to 700 MHz without splitting individually optimized circuits corresponding to each frequency band and using no external board components. This is the first suggestion of a fully integrated SK filter-based tunable filter to cover VHF/UHF bands through a hardware re-configurability without increasing the tuning ratio of the switched capacitor array, while providing an optimum HRR performance for corresponding operating frequencies in conjunction with harmonic rejection mixer (HRM). In addition, it proposes a hardware efficient re-configurable balun-LNA to operate as a wideband feedback LNA at sub-GHz and a narrowband ISDLNA at 2.4 GHz without the use of external input matching circuits. In the measurement, the proposed front-end achieves an average power gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{S}_{{21}}$ </tex-math></inline-formula> ) of 25.9 dB, NF of < 4.25 dB, and in-band input-referred third-order intercept point (IIP3) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;\!\!\!-12.8$ </tex-math></inline-formula> dBm over the tuning range from 50 MHz to 700MHz. The proposed tunable filter shows the frequency-optimized HRR from 10 dBc to 26 dBc over the tuning range while greatly reducing a silicon area. At 2.4 GHz band, it shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{S}_{{21}}$ </tex-math></inline-formula> of 14.7 dB, NF of 3.2 dB, and in-band IIP3 of −4.5 dBm. The die area of the proposed circuit, excluding I/O PADs and the measurement output buffer, is less than 2.0 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the front-end working at sub-GHz and 2.4 GHz bands is 33.6 mW and 5.1 mW respectively.

A 17-mW 0.5–1.5-GHz Bandwidth TIA Based on an Inductor-Stabilized OTA With 35–42-dBm In-Band IIP3

A transimpedance amplifier (TIA) is presented for 5G and future mobile standards. The bandwidth of the TIA can be programmed from 500 MHz to 1.5 GHz. The operational transconductance amplifier (OTA) is designed combining feedforward compensation and inductive peaking, to ensure loop stability and obtain high loop gain with low-power dissipation. TSMC 28-nm HPC technology was used to implement a test chip. With a power dissipation of 17 mW, the TIA achieves an in-band IIP3 ranging from 35 to 42 dBm and output integrated noise of 300 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> Vrms.

Design of High-Linearity Mixer-First Receivers for mm-Wave Digital MIMO Arrays

A 10–35-GHz mixer-first receiver is proposed for use in digital multiple-input–multiple-output (MIMO) arrays. Techniques are proposed to enhance the linearity of such receivers, both at baseband and the RF mixer switches. Techniques to mitigate charge sharing due to local oscillator (LO) overlap are also proposed. Detailed simulation results are provided to illustrate the benefits of these techniques. An integrated circuit prototype is fabricated in 28-nm bulk CMOS and fully characterized. The receiver has built-in programmability to tradeoff gain for linearity. The receiver achieves a peak in-band IIP3 of +14.1 dBm, a peak gain of 14.5 dB, and a noise figure of 12.5 dB, in its nominal setting.

Analysis and Design of Submilliwatt Interference-Tolerant Receivers Leveraging N-Path Filter-Based Translational Positive Feedback

A low-power 2.2-2.4-GHz receiver front end for Internet-of-Things (IoT) applications is presented. The front end consists of a capacitively cross-coupled common-gate low-noise amplifier (CC-CGLNA), with translational positive feedback from baseband to RF through a four-phase switching mixer, providing RF filtering and matching, in conjunction with a 1:4 transformer. A detailed analysis of the architecture is presented, highlighting the design tradeoffs between noise, out-of-band filtering, and power. A prototype integrated circuit, fabricated in 28-nm CMOS, consumes 580 μW of power for the entire receiver front end. With this submilliwatt power consumption, it achieves a noise figure (NF) of 11.9 dB, an in-band IIP3 of -6.5 dBm, and an out-of-band IIP3 of +3.3 dBm.

High-Q, High-Rejection Ratio Complex Second-Order Charge-Sampling Switched gm-C Semi-Passive Band-Pass Filter

In this paper, a complex second-order charge-sampling switched [Formula: see text]-[Formula: see text] semi-passive band-pass filter (BPF) is presented which by using the technique of increasing the number of input signal phases without the need to increase the number of clock phases and switches, has been improved out-of-band rejection, near-band rejection and the quality factor of the filter. In addition to the tunable bandwidth and center frequency that can be tuned independently, the proposed filter provides a very high linearity and consumes low power. Designed and simulated in a [Formula: see text]m standard CMOS technology, this filter operating at 1[Formula: see text]GS/s sampling rate has an adjustable center frequency of 11.68–28.5[Formula: see text]MHz and a tunable bandwidth of 1.8–8.74[Formula: see text]MHz. Also, the out-of-band rejection varies from 37[Formula: see text]dB to 39[Formula: see text]dB in an offset frequency of 3 fc. The in-band IIP3, power consumption and input-referred noise are 28[Formula: see text]dBm, 5[Formula: see text]mW and 13.8–18.8[Formula: see text]nv/sqrt (Hz), respectively

A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications

In this article, we propose a baseband noise-canceling receiver architecture to increase in-band linearity. A key feature of the architecture is that all active circuits are in baseband, including the low-noise transconductance amplifier (LNTA). The LNTA operating at baseband frequencies allows the use of feedback to increase the linearity. This article analyzes a tradeoff that exists between in-band linearity and noise in mixer-first receivers and shows how the proposed architecture breaks such tradeoff. The receiver targets high IF bandwidths, enabled by a transimpedance amplifier (TIA) composed of an OpAmp using only inverters. This article describes the stabilization mechanism of this OpAmp with a unity-gain bandwidth (UGB) of 7.6 GHz. The receiver is fabricated in 22-nm FDSOI CMOS. The measured results show an in-band IIP3 of > 9 dBm for an IF bandwidth of 175 MHz with sub-5-dB noise figure (NF) across 1-6-GHz local oscillator (LO) frequencies.

A Reconfigurable Passive Mixer-Based Sub-GHz Receiver Front-End for Fast Spectrum Sensing Functionality

A reconfigurable parallel mixing subharmonic mixer (SHM)-based time-interleaved RF channelizer is proposed for fast spectrum sensing. The reconfigurable mixer operates as a double-balanced mixer (DBM), a double-balanced mixer with harmonic rejection (DBM&HR), and an SHM. In contrast to conventional spectrum sensing receivers to detect RF frequency bands by sweeping local oscillator (LO) frequencies, the proposed receiver scans multiple frequency bands quickly through mode change of the reconfigurable mixer. The LO generation circuit employs a voltage subtractor-based phase adder and provides highly accurate 25% duty-cycle octet-phase LO signals. The front-end implements a high LO harmonic rejection ratio (HRR) in order to avoid signal corruption by LO harmonic mixing during spectrum sensing. In experiments, the proposed receiver achieves <; 40.3 dB conversion gain, <; 6.6 dB noise figure (NF), > -35.8 dBm in-band input-referred third-order intercept point (IIP3), > -22.3 dBm out-of-band IIP3, and an average 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> LO HRR of 43 dB over 300-800 MHz in DBM&HR mode. Over 600-1200 MHz in SHM mode, it shows >31.8 dB conversion gain, <; 10.4 dB NF, > -30.9 dBm in-band IIP3, and > -20.1 dBm out-of-band IIP3. The switching time between DBH&HR and SHM modes is approximately 135 ns. The power dissipation is 24.7 mW from a 1.2 V supply voltage.

Design of Low-Power Sub-2.4 dB Mean NF 5G LNAs Using Forward Body Bias in 22 nm FDSOI

This article presents K/Ka-band low-noise-ampli- fiers (LNAs) for 5G front ends. The use of forward body bias (FBB) in fully depleted silicon-on-insulator (FDSOI) devices is studied and utilized to improve the LNA performance under reduced supply voltage and dc power ( $P_{\mathrm{ dc}}$ ). Design procedures targeting high linearity, low noise, and high gain are provided. The two-stage common-source LNA (CS-LNA) achieves sub-2.1 dB mean NF, 20.1 dB peak gain, 9 GHz 3 dB bandwidth (BW) from 19.5 to 28.5 GHz, and an in-band IIP3 of 0 dBm with 9.6 mW $P_{\mathrm{ dc}}$ . The single-stage cascode LNA (CAS-LNA) achieves over 10 dB gain, 11 GHz 3 dB BW, and an IIP3 of 7.5 dBm for a 2.2 dB mean NF. The two-stage CAS-LNA has 28.5 dB peak gain, 4 GHz BW, and 2.25 dB mean NF for 20 mW $P_{\mathrm{ dc}}$ . In the low-power mode, the CS-LNA operates at 0.4 V with $P_{\mathrm{ dc}}$ of 3.2 mW, 16.9 dB gain, and less than 2.2 dB mean NF, while the two-stage CAS-LNA achieves 2.4 dB NF and 23 dB gain for 5.5 mW. Also, ultralow-power operation and sub-3 dB NF are possible with the CS-LNA at 0.2 V/1 mW with 12 dB gain and for the CAS-LNA at 0.4 V/2.4 mW with 17.7 dB gain. To the best of our knowledge, the single-stage CAS-LNA shows the highest IIP3 at 28 GHz compared with the published CMOS work. The two-stage FBB CS and CAS designs have the lowest voltage supply, $P_{\mathrm{ dc}}$ , and best Figure of Merit (FoM) for mm-waves 5G LNAs in the low-power mode.

A PVT-Resilient, Highly-Linear Fifth-Order Ring-Oscillator-Based Filter

This paper introduces a new class of ring oscillator (RO)-based filters that address linearity and process variance limitation of existing RO-based filters. A highly-linear process-tolerant RO filter topology is achieved by imitating the widely known active-RC topology in the phase domain. We propose utilizing a set of frequency detectors (FDs) and phase detectors (PDs) to extract both the frequency and phase information of an inverter-based RO to synthesize active filters in a way similar to integrator-based active-RC filters, which are synthesized using a set of capacitors and resistors, respectively. A zero compensation technique is proposed to extend the achievable bandwidth of the proposed topology. Also, a delay-locked loop (DLL)-based tuning scheme is introduced to achieve resilience over PVT variations. A prototype 5th-order, 2–22 MHz continuous-time Butterworth filter is presented in 130 nm CMOS technology to demonstrate the proposed topology. The filter consumes 6.2–8.9 mA from a 1 V supply and achieves 26.2 dB in-band IIP3. The filter achieves bandwidth variation less than ±3.5% over a temperature range of −40 °C to 85 °C and supply voltage range of 0.9–1.2 V.

A 16 Path All-Passive Harmonic Rejection Mixer With Watt-Level In-Band IIP3 in 45-nm CMOS SOI

This work presents an all-passive harmonic rejection mixer (HRM) with watt-level in-band IIP3. The HRM operates in the voltage mode using resistors to scale the voltages of the different paths across the frequency cycle and therefore, attains very high linearity. The passive HRM employs a non-overlapping clock generation chain combined with duty cycle control circuit to trim the rise and fall times of the individual paths, and maintains the harmonic rejection ratio (HRR) over the frequency band. Two 0.13-3 GHz 16-path HRM chips are fabricated in 45-nm CMOS silicon-on-insulator (SOI) technology using thin and thick-oxide devices, respectively, with 80-MHz IF bandwidth and a core area 0.06 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The thick-oxide HRM achieves a HRR >35 dBc for all harmonics up to 3 GHz with a conversion loss of 8-10 dB, while the in-band IIP3 is 24-31 dBm and IP1 dB is 11-13 dBm for an RF of 0.5-3 GHz. To the authors knowledge, the all-passive 16-path HRM achieves the highest reported in-band IIP3 and IP1 dB.

A Four-Phase Passive Mixer-First Receiver With a Low-Power Complementary Common-Gate TIA

This paper presents a four-phase passive mixer-first receiver using a common-gate (CG) trans-impedance amplifier (TIA), instead of a conventional shunt-feedback amplifier. The four-transistor TIA used in this work combines current-reuse with cross-coupled $g_{m}$ -boosting to achieve a reduced noise figure (NF) at low power levels. Moreover, complementary derivative-superposition (CDS) linearization within the TIA helps to improve the linearity with no additional power overhead. A prototype receiver is implemented in a 180 nm CMOS technology. The receiver operates from 0.3 to 1.3 GHz with a conversion gain of 21.9 dB. In measurements, the receiver achieved a noise figure of 5.8 dB and an in-band (IB) IIP3 of +7.2 dBm while consuming 0.34 mW power per TIA at 1 GHz. The measured spurious-free dynamic range (SFDR) at 1 GHz is 76.9 dB.

A Charge-Domain Switched-Gm-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique

A highly reconfigurable charge-domain switched- $g_{\mathrm {m}}$ -C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge-sharing technique is proposed. It uses only switches, capacitors, linearity-enhanced $g_{\mathrm {m}}$ -stages and digital circuitry for a 3-phase non-overlapping clock scheme. Flexible tunability in both center frequency and −3dB bandwidth is achieved with a scaling-compatible implementation. A 4th-order BPF prototype operating at a 1.2GS/s sampling rate is designed with a cascade of two reconfigurable biquad stages in a 65nm LPE CMOS process. A tunable center frequency of 35–70MHz is measured with programmable bandwidths and a maximum stop-band rejection of 72dB. The measured in-band IIP3 is +12.5dBm. The filter prototype consumes 7.5mW total power from a 1.2V supply voltage, and occupies an active area of 0.17mm2.

A New Tune-Dependent Multiple-Gated Transistor Linearization Technique

In this paper, a new multiple-gated transistor (MGTR) linearization technique is presented. To simultaneously keep linearity and tuning capability of proposed operational transconductance amplifier (OTA), the auxiliary transistors which are employed for [Formula: see text] cancellation of differential pair (DP) stage are body-driven through a tune-dependent voltage. By this way, the third-order nonlinearity of DP is reduced for a wide range of transconductance values from 5.1 to 35.6[Formula: see text][Formula: see text]A/V. The OTA works with 1.2[Formula: see text]V supply voltage and its power consumption changes between 137.4 and 156[Formula: see text][Formula: see text]W at the entire tuning range. For [Formula: see text][Formula: see text][Formula: see text]A/V ([Formula: see text][Formula: see text]V) and for 0.6[Formula: see text][Formula: see text] input voltage, the simulation results show 6[Formula: see text]dB reduction in the total harmonic distortion (THD) of proposed OTA when the MGTR linearization technique is used and 15[Formula: see text]dB reduction when the tune-dependent body driving is also utilized. The proposed OTA is employed in a third-order low-pass Butterworth filter which is tunable from 2 to 18[Formula: see text]MHz. The in-band IIP3 of filter is 16.9 and 12.4[Formula: see text]dBm, respectively, for 2 and 18[Formula: see text]MHz cutoff frequencies while the two-tone input voltage is applied at 1[Formula: see text]MHz.

Low-power fully monolithic MICS band receiver for 402-405 MHz implantable devices

ABSTRACTA 402–405MHz fully monolithic Radio Frequency (RF) low-Intermediate Frequency (IF) receiver is presented. The proposed low-power RF receiver consists of a differential Common gate-Common Source Low-Noise Amplifier (CG-CS LNA) with a positive–negative feedback technique, passive mixer, fully integrated Voltage Controlled Oscillator (VCO), and an IF Variable Gain Amplifier (VGA). To achieve a wide tuning range while keeping a low gain (Kvco), the VCO has 16 bands selectable by a 4-bit digital control. The complete receiver prototype is implemented in a 0.13μm CMOS process and occupies 0.625 mm2 active chip area. The receiver consumes only 3.76 mW of power from a 1.2 V power supply and has a gain of 45 dB and a noise figure of 13.6 dB (integrated from 20 Hz to 0.5 GHz). The design achieves an in-band IIP3 of 2 dBm, IIP2 better than 44 dBm. It presents a 3-dB IF bandwidth of 3 MHz with −80 dBm sensitivity.

A Flexible Phased-Array Architecture for Reception and Rapid Direction-of-Arrival Finding Utilizing Pseudo-Random Antenna Weight Modulation and Compressive Sampling

The direct space-to-information converter (DSIC) unifies conventional delay-and-sum analog conventional beamforming (CBF) with compressive sampling (CS) rapid direction-of-arrival (DOA) finding into a single, reconfigurable phased-array receiver architecture. Where current CBF-based DOA scanners need to exhaustively search through multiple DOA angles, the DSIC is able to receive energy from all possible angles by modulating its antenna weights psuedo-randomly. The DSIC RF-ASIC can operate from 1 to 3 GHz, was fabricated in 65-nm CMOS, and includes eight direct-conversion paths each delivering 32-dB conversion gain, 3.3-dBm in-band IIP3, and 6.4-dB NF while consuming 19.8 mW from 1.2 V. The DSIC RF-ASIC has two modes of operation, CS-DOA and CBF-Reception and can switch between them in less than $1~\mu \text{s}$ . In CS-DOA mode, the DSIC RF-ASIC finds the DOA of a single signal in $1~\mu \text{s}$ consuming 158 nJ which is 4 $\times $ faster and 1.5 $\times $ less energy than a comparable CBF-based DOA scanner.

OTA-based switchable gain and order multi-standard receiver analog baseband chain

In this paper, we propose a digital programmable OTA-based multi-standard receiver for analog baseband chain. It consists of a switchable-order low-pass filter and two programmable gain amplifiers (PGAs). The low-pass filter has a cutoff frequency that can be digitally tuned from 1 MHz to 10.2 MHz. Thus, it covers Bluetooth, UMTS, DVB-H and IEEE 802.11a/g standards. The gain of each PGA can be varied from 0 dB to 35 dB with a gain step of 5 dB. The proposed multi-standard receiver is designed and simulated in 90 nm CMOS technology under ±0.6 V supply voltage. The overall simulation results show a variable gain from 0 dB to 70 dB, switchable-order (2nd/4th/6th) frequency response, in-band IIP3 of 21.9 dBm, and input referred noise of 102.6 nV/Hz at 1 MHz with total power consumption of 11.77 mW.

0.18 mW/pole inverter‐based G m ‐C bandpass filter with automatic frequency tuning

A low-power Gm-C filter with the elliptic prototype targeting wireless application of the IEEE 802.15.4 (ZigBee) standard is presented. A modified inverter-based Gm cell is proposed to increase the current efficiency. Due to the tail current source, this Gm cell also shows better common-mode rejection and power supply rejection performance than traditional operational transconductance amplifier (OTA) structure. The filter is implemented in a 65 nm CMOS process. It achieves a figure of merit of 0.01 fJ with a power consumption of 0.18 mW/pole from a 1.2 V supply voltage. It provides stopband attenuation better than 40 dB, and an in-band IIP3 of 9 dBm. An automatic frequency tuning circuit based on sine-wave PLL method is introduced to compensate for the process variations. The centre frequency and bandwidth can be simultaneously tuned to satisfy the specifications. They are also stable over the process variations with only 2.3% deviation.

Design of 1.8-mW PLL-Free 2.4-GHz Receiver Utilizing Temperature-Compensated FBAR Resonator

This paper presents a 1.8-mW 2.4-GHz channelized receiver for ISM-band applications. Unlike traditional ISM-band radios which typically require a phase-locked loop (PLL) for channelization, we propose a modified sliding-IF receiver architecture with a suitable local oscillator (LO) frequency plan utilizing a temperature-compensated thin film bulk acousticwave resonator (FBAR). This strategy completely eliminates the need for a PLL by directly dividing down the fixed FBAR oscillator frequency. An inductor-less current-reuse balun LNA is proposed allowing a low-power wideband matching as well as noise cancelling. The frequency conversion is achieved by a hybrid mixer, which stacks a switching mixer on a switched-gm mixer for current reuse. It also features good voltage headroom and common-mode noise rejection. The FBAR-based Colpitts oscillator achieves the phase noise of -144 dBc/Hz at 3.5-MHz offset. The measured RX gain, noise figure, and in-band IIP3 are 57.8 dB, 15.7 dB, and -18.5 dBm, respectively, without external crystal and on-chip inductors, which allows us to reduce the size and weight of the receiver system. It dissipates 0.86 mW (RX) and 0.92 mW (LO) from a single 1-V supply.

A Low-Power Interference-Tolerance Wideband Receiver for 802.11af/ah Long-Range Wi-Fi With Post-LNA Active &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$N$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Path Filter

A low-power interference-tolerance wideband receiver with post-LNA active N-path filter for RF channel selection is proposed for 802.1af/ah long-range Wi-Fi standards. By leveraging gain, noise, and filtering characteristics among the wideband LNA, high-Q active N-path filter, and reconfigurable analog baseband circuits, the proposed receiver achieves high gain, low noise, and high linearity with low power dissipation. The receiver provides narrow-bandwidth RF filtering with a small chip area. Implemented in a 40-nm CMOS process with the chip size of 1.1 mm $\times2.25$ mm, the full receiver shows a conversion gain of 84 ± 1 dB and achieves noise figure from 3.4 to 3.9 dB in subgigahertz frequency bands. The measured in-band IIP3, out-of-band IIP3, and out-of-band IIP2 are −5.9, −0.5, and +62.5 dBm, respectively. The proposed receiver dissipates an average power of 41 mW.