Improve Power Efficiency Research Articles

A chaos-based true random number generator based on OTA sharing and non-flipped folded Bernoulli mapping for high-precision ADC calibration

An operational amplifier sharing (op-amp sharing), non-flipped folded Bernoulli mapping chaos-based true random number generator (TRNG) is proposed in this paper. Based on the concept of op-amp sharing for non-flipped folded Bernoulli mapping, the number of stages is reduced from two stages to one, which improves power efficiency of the system. Among them, a novel transconductance enhancement recycling amplifier is adopted for power reduction. The entire system has been implemented in a standard 180 nm process with power supply of 1.2V, and the output speed of random number is 500k Bits/s with power consumption of only 4.68 μW. The TRNG system is verified over a wide range of process and temperature variations, including TT corner 25 °C, FF corner 0 °C, and SS corner 85 °C with post-layout simulation. All the generated random bits pass National Institute of Standards and Technology (NIST) SP800-22 randomness tests successfully.

System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System

Despite being employed in numerous efforts to improve power delivery efficiency, the integrated voltage regulator (IVR) approach has yet to be evaluated rigorously and quantitatively in a full power delivery system (PDS) setting. To fulfill this need, we present a system-level modeling and design space exploration framework called Ivory for IVR-assisted power delivery systems. Using a novel modeling methodology, it can accurately estimate power delivery efficiency, static performance characteristics, and dynamic transient responses under different load variations and external voltage/frequency scaling conditions. We validate the model over a wide range of IVR topologies with silicon measurement and SPICE simulation. Finally, we present two case studies using architecture-level performance and power simulators. The first case study focuses on optimal PDS design for multi-core systems, which achieves 8.6% power efficiency improvement over conventional off-chip voltage regulator module– (VRM) based PDS. The second case study explores the design tradeoffs for IVR-assisted PDSs in CPU and GPU systems with fast per-core dynamic voltage and frequency scaling (DVFS). We find 2 μs to be the optimal DVFS timescale, which not only reaps energy benefits (12.5% improvement in CPU and 50.0% improvement in GPU) but also avoids costly IVR overheads.

Experimental evaluation of medium-voltage cascode gallium nitride (GaN) devices for bidirectional DC-DC converters

Wide bandgap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), exhibit superior physical properties and demonstrate great potential for replacing conventional silicon (Si) semiconductors with WBG technology, pushing the boundaries of power devices to handle higher blocking voltages, switching frequencies, output power levels, and operating temperatures. However, tradeoffs in switching performance and converter efficiency when substituting GaN devices for Si and SiC counterparts are not well-defined, especially in a cascode configuration. Additional research with further detailed investigation and analysis is necessitated for medium-voltage GaN devices in power converter applications. Therefore, the aim of this research is to experimentally investigate the impact of emerging 650/900 V cascode GaN devices on bidirectional dc-dc converters that are suitable for energy storage and distributed renewable energy systems. Dynamic characteristics of Si, SiC, and cascode GaN power devices are examined through the double-pulse test (DPT) circuit at different gate resistance values, device currents, and DC bus voltages. Furthermore, the switching behavior and energy loss as well as the rate of voltage and current changes over the time are studied and analyzed at various operating conditions. A 500 W experimental converter prototype is implemented to validate the benefits of cascode GaN devices on the converter operation and performance. Comprehensive analysis of the power losses and efficiency improvements for Si-based, SiC-based, and GaN-based converters are performed and evaluated as the switching frequency, working temperature, and output power level are in-creased. The experimental results reveal significant improvements in switching performance and energy efficiency from the emerging cascode GaN devices in the bidirectional converters.

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The FoMS,SNDR (= SNDR + 10log10BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.

Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

Advanced OTFS communication system with compact spectrum and power efficiency improvement

SummaryOrthogonal time frequency space (OTFS) modulation technique is one‐step more precoded system of the conventional orthogonal frequency division multiplexing (OFDM) system, i.e., a double precoded system. The OTFS system was suggested especially for the robust and reliable high‐speed vehicle communications and massive multiple‐input multiple‐output (MIMO) systems. Nevertheless, this basic OTFS system has serious problems: high out‐of‐band (OOB) power emission and high peak‐to‐average power ratio (PAPR). This high OOB power spectrum requires a very wide guard band that can produce a great loss of frequency utilization efficiency, and the power efficiency becomes very poor due to this high PAPR problem. Therefore, in this paper, in order to mitigate these drawbacks, an advanced OTFS communication system is proposed to show the compact OOB power spectrum and power efficiency improvement. This system can be designed by discrete Fourier transform (DFT)‐spread windowing and restructuring‐OTFS (DFT‐Spread WR‐OTFS) scheme that can reduce PAPR by 2.1 dB, 0.5 dB, 1.7 dB, and 1.8 dB compared to the conventional OFDM, DFT‐Spread OFDM, basic OTFS and WR‐OTFS schemes, respectively. Consequently, the efficiency of the high power amplifier (HPA) is improved due to the low PAPR of the proposed system. In addition, we comprehensively evaluate the impact of PAPR reduction performance on the OOB power spectrums and bit error rate (BER) performance of each system in HPA linear and nonlinear environments. Simulation results verify that the power spectrums and the BER performance of the proposed system are better than the conventional schemes in HPA nonlinear environments.

Power efficiency improvement in cladding pumping technique for annular 12-core doped fiber amplifier using vortex lens and beam fanner

Cladding pumping is a common method to amplify signal channels in space-division multiplexing (SDM) systems. A high-power laser pump is directly launched to multi-core doped fiber (MCDF), and depending on the arrangement of cores in the MCDF, a small fraction of power goes to each core and amplifies the signal. Therefore, we have designed two diffractive optical elements, vortex lens (VL) and beam fanner (BF), to properly form the transverse pump distribution and increase pump power efficiency. Phase-only approximation and angular spectrum (AS) based methods are used to design the elements. We have found that using VL and BF allowed a significant increase in the pump power efficiency compared to direct cladding pumping.

Modeling and Analysis of High-Performance Triple Hole Block Layer Organic LED Based Light Sensor for Detection of Ovarian Cancer

In this paper a novel triple hole block layer (HBL) structure of the OLED is proposed that depicts an enhanced luminescence of 25285 cd/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with an improvement of 47% over multilayered OLED architecture. It also owes 74% improvement in luminous power efficiency. An in-depth numerical analysis based on Poisson and drift diffusion equation is undertaken and validated against the internal device analysis. The analysis results highlight an enhanced recombination rate within the proposed device. High electron injection and efficient hole blocking contributes to improved recombination rate. Triple HBL OLED is therefore used for diagnosis of ovarian cancer. The device illustrated good response towards varying wavelengths generating a maximum photo current value of 93 mA. A healthy person can be differentiated from an oncological cancer patient based on fluorescence produced by their urine. The fluorescence values for healthy person and oncological cancer patient are in the range of 420 and 440 nm, correspondingly. The cathode current produced by OLED corresponding to these two wavelengths are 5 and 1 mA respectively. Hence, the proposed device can successfully diagnose the ovarian cancer patient. Further, the methodology proposed for diagnosis of ovarian cancer can help in developing a portable, flexible low cost biomedical sensor.

Application of ZnGa₂O₄:Mn Down-Conversion Layer to Increase the Energy-Conversion Efficiency of Perovskite Solar Cells.

The perovskite solar cell is capable of energy conversion in a wide range of wavelengths, from 300 nm to 800 nm, which includes the entire visible region and portions of the ultraviolet and infrared regions. To increase light transmittance of perovskite solar cells and reduce manufacturing cost of perovskite solar cells, soda-lime glass and transparent conducting oxides, such as indium tin oxide and fluorine-doped tin oxide are mainly used as substrates and light-transmitting electrodes, respectively. However, it is evident from the transmittance of soda-lime glass and transparent conductive oxides measured via UV-Vis spectrometry that they absorb all light near and below 310 nm. In this study, a transparent Mn-doped ZnGa₂O₄ film was fabricated on the incident surface of perovskite solar cells to obtain additional light energy by down-converting 300 nm UV light to 510 nm visible light. We confirmed the improvement of power efficiency by applying a ZnGa₂O₄:Mn down-conversion layer to perovskite solar cells.

Research On Power Dissipation of ERSFQ Circuits

Energy-efficient rapid single flux quantum (ERSFQ) circuits are often considered to have two working states including ERSFQ (zero static power dissipation) and RESFQ (resistive energy-efficient SFQ) state. In our previous research, a new working state called MIDSFQ state has been also found in which the biasing JJs cannot return to the non-voltage state after the dynamic process. Both the RESFQ and MIDSFQ states result in extra power dissipation and should be avoided if possible. In this paper, we investigate the characteristics of these three states and explain the working principle of the MIDSFQ state using the hysteresis effect. We obtain an optimization scenario to eliminate the MIDSFQ state and furthermore, a simple but effective method to improve power efficiency of ERSFQ circuits.

Design and Simulation of Novel 3-DOF Spherical Voice Coil Motor

Multi-DOF motion is realized in the eyes and joints of robots mostly through the combination of multiple one-degree-of-freedom (1-DOF) motors. However, this results in reduced efficiency, a large volume, reduced response speed, and inaccurate positioning. To solve these problems, this study proposes a novel 3-DOF spherical voice coil motor (VCM). In this VCM, 16 coils and a radially oriented ring magnet are used to generate a Lorentz force to achieve motion. In particular, coils for Z-axis rotation are sandwiched between the coils for X- and Y-axis rotation. Furthermore, the proposed VCM can achieve 360° rotation about the Z-axis. The commercial software ANSYS was used to design and verify the performance of the proposed VCM. Simulation results indicate that this VCM affords improved power efficiency because only a suitable combination of coils, rather than all coils, needs to be powered on. The results demonstrate the feasibility of the proposed 3-DOF spherical VCM.

An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks

Designing hardware accelerators for convolutional neural networks (CNNs) has recently attracted tremendous attention. Plenty of existing accelerators are built for dense CNNs or structured sparse CNNs. By contrast, unstructured sparse CNNs can achieve higher compression ratio with equivalent accuracy. However, their corresponding hardware implementations generally suffer from load imbalance and conflict access to on-chip buffers, which results in under utilization of processing elements (PEs). To tackle these issues, we propose a hardware/power-efficient and highly flexible architecture to support both unstructured and structured sparse CNNs with various configurations. Firstly, we propose an efficient weight reordering algorithm to preprocess compressed weights and balance the workload of PEs. Secondly, an adaptive on-chip dataflow, namely hybrid parallel (HP) dataflow, is introduced to promote weight reuse. Thirdly, the partial fusion scheme, which was first introduced in one of our prior works, is incorporated as the off-chip dataflow. Benefited from dataflow optimizations, the repetitive data exchanges between on-chip buffers and external memories are significantly reduced. We implement the design on the Intel Arria10 SX660 platform and evaluate with MobileNet-v2, ResNet-50, and ResNet-18 on ImageNet dataset. Compared to existing sparse accelerators on FPGAs, the proposed accelerator can achieve $1.35\sim 1.81\times $ improvement in power efficiency with the same sparsity. Compared to prior dense accelerators, this accelerator can achieve an improvement of $1.92\sim 5.84\times $ in DSP efficiency.

Rome to Milan, AMD Continues Its Tour of Italy

AMD’s recently released EPYC 7003 series CPUs (codename Milan) deliver performance and power efficiency improvements over its previous generation of data center CPUs (codename Rome). Various architectural improvements were made such as an uplift from the Zen 2 core to the Zen 3 core, unifying the L3 cache, and adding security features. Relative to the competition, AMD’s latest data center CPUs are very competitive. However, the looming threat of vertical integration plagues the entire market.

Impact of Dielectrics in SOI FinFET for Lower Power Consumption in Punch-through Current-based Local Thermal Annealing

Impact of device geometric structures and materials is discussed to improve power efficiency of punch-through current based electro-thermal annealing (ETA). Various sensitivities that affect device temperature during ETA are extracted and compared. Then, dielectric engineering in terms of thermal conductivity and thermal isolation is suggested for better power management. Finally, time-dependent characteristics with various thicknesses of buried dielectric layer are discussed to improve annealing speed. As a result, the contents of this paper provide a guide to better application of ETA.

High Step-Up Converter Based on Non-Series Energy Transfer Structure for Renewable Power Applications.

In this paper, a high step-up boost converter with a non-isolated configuration is proposed. This configuration has a quadratic voltage gain, suitable for processing energy from alternative sources. It consists of two boost converters, including a transfer capacitor connected in a non-series power transfer structure between input and output. High power efficiencies are achieved with this arrangement. Additionally, the converter has a common ground and non-pulsating input current. Design conditions and power efficiency analysis are developed. Bilinear and linear models are derived for control purposes. Experimental verification with a laboratory prototype of 500 W is provided. The proposed configuration and similar quadratic configurations are compared experimentally using the same number of components to demonstrate the power efficiency improvement. The resulting power efficiency of the prototype was above 95% at nominal load.

発電効率・耐久性を向上した家庭用固体酸化物形燃料電池 「エネファームtype S」

発電効率・耐久性を向上した家庭用固体酸化物形燃料電池 「エネファームtype S」

Cloud-backed mobile cognition

Low-power embedded technology offers a roadmap for enabling deep learning (DL) applications in mobile scenarios, like future autonomous vehicles. However, the lack of breakthrough power efficiency improvements can jeopardize the realization of truly “cognitive” mobile systems that meet real-time deadlines. This work focuses on the new generation cloud-backed mobile cognition system architecture where vehicles execute DL applications with dynamic assistance from the cloud. We unveil opportunities for power-efficient inferencing at the edge through a technique that balances inference execution across the cloud and the vehicle. This level of adaptation results in significant power efficiency improvements compared to all or nothing solutions, where inferences execute either completely on the vehicle or completely in the cloud. In addition, the cloud can have an active role in helping the vehicle to improve its DL capabilities by communicating relevant model updates, with up to 63% bandwidth savings and negligible accuracy degradation when the proposed relevance-driven federated learning technique is used. Finally, the cloud-backed mobile cognition concept is extended to the case of “flying clouds” where vehicles connect to flying drones that provide services while in flight. Although their capabilities are not on par with the stationary cloud, the flying cloud reduces services’ latency significantly and enables critical functionalities.

A low power low noise analog front-end for ECG recording

This work presents a power-efficient and noise-efficient amplifier for ECG recordings. To improve power efficiency, all the transistors in the proposed amplifier is designed in sub-threshold region which gives high g $$_m$$ /I $$_D$$ ratio. To improve noise efficiency, inverter-based differential input stage is used in this proposed operational transconductance amplifier as it reduces noise by a factor of $$\sqrt{2}$$ when compared to it’s non-inverter based counterpart. In order to decrease flicker noise, large transistors are used in the input stage. Class A–B structure is used in the output stage for achieving high g $$_m$$ /I $$_D$$ ratio and for large output swing range. In 180 nm process the amplifier consumes 477 nW DC power from 1.8 V supply which indicates 7.5% decrease in power consumption when compared to recently reported papers. This amplifier achieves a noise efficiency of 2.68. Common mode rejection ratio and power supply rejection ratio is estimated as 98.5 dB and 104.5 dB respectively.

Contactless Power Transfer for Rail-Guided Vehicles With Power Equalization and Efficiency Improvement Considerations

This article proposes a contactless power transfer for rail-guided vehicles with power equalization and efficiency improvement considerations. This study is motivated since the rail-guided vehicles may encounter the power imbalance and low efficiency during the power transfer under a multireceiver environment. Therefore, the article is devoted to designing an approach of evenly dispatching power among receivers as well as developing a tracking compensation technique to search the maximum power-transmitting efficiency under different number of receiving modules. Through this proposed method, the constant power output, power equalization, and efficiency improvement are all achieved. Circuit derivation, frequency response, and resonance features are all made. A hardware circuit is also realized with different tests carried out under various scenarios. The maximum efficiency of this system is recorded to be 90.3%, supporting the practicality of the method. Experimental outcome gained from this study is beneficial for on-rail charging applications.

A low-power embedded poly-Si micro-heater for gas sensor platform based on a FET transducer and its application for NO2 sensing

• A FET-type gas sensor platform with low power consumption is proposed. • The platform offers the best power efficiency (e.g. 300 ℃ at 1.63 mW) among the reported gas sensors with external heaters. • Electrode metals with low thermal conductivity and an efficient heat insulating air gap design improve power efficiency. • The platform is sensitive and advantageous for low-concentration gas detection. Gas sensors are commercialized and widely applied in various fields. Existing commercial sensors, however, have limitations in terms of power consumption. In this work, we propose a new design guideline of the FET-type gas sensor platform to significantly improve the power efficiency of the embedded poly-Si micro-heater. The fabricated sensors are capable of low power operation while maintaining high response and stability. To our knowledge, the embedded micro-heater of the proposed platform provides the best power efficiency (e.g. 300 ℃ at 1.63 mW) among reported gas sensors with external heaters. By adopting electrode metals with low thermal conductivity (Ti/TiN instead of Cr) in contact with the heater and an efficient heat insulating air gap design (increasing air gap length under the electrode from 0 μm to 28 μm), we can increase the heater temperature by 63 % at the same power consumption. Also, the proposed platform is more sensitive and advantageous for low-concentration gas detection compared to the reported FET-type platform using hot chuck that increases the temperature of the entire sensor.