Improved Phase Noise Performance Research Articles

0.18-μm CMOS process 40 MHz–4.41 GHz frequency synthesizer with high linearity low phase noise varactor-reconstruction LC-VCO

A 40 MHz–4.41 GHz fractional-N frequency synthesizer (FS) with varactor-reconstruction VCO (VRVCO) fabricated in the standard 0.18-μm CMOS process is demonstrated. In the conventional VCO, owing to non-linearity of varactor and parasitic effects of switched-MOSFET, the top and bottom of the tuning curves show nonlinearity. The novel design of VRVCO for tuning sensitivity base on series-shunt hybrid capacitor-varactor part and optimized switched-capacitor bank is incorporated into the 4.41 GHz FS design to reduce the variation of the VCO gain, realize high linearity tuning curves and improve phase noise performance. Furthermore, a noise reduction topology is adopted to decrease phase noise of VRVCO. Simulated results show the proposed VRVCO can improve linearity of tuning frequency over the entire tuning range. The measured results show the overall tuning range exceeds 115% from 1.92 to 4.41 GHz including three VRVCOs with high linearity (fine-tuning sensitivity: 131%, coarse-tuning sensitivity: 106%) and the phase noise is −120dBc/Hz at 1 MHz offset from the carrier frequency of 4.41 GHz.

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Electrically connected spin-torque oscillators array for 2.4\u2009GHz WiFi band transmission and energy harvesting

The mutual synchronization of spin-torque oscillators (STOs) is critical for communication, energy harvesting and neuromorphic applications. Short range magnetic coupling-based synchronization has spatial restrictions (few µm), whereas the long-range electrical synchronization using vortex STOs has limited frequency responses in hundreds MHz (<500 MHz), restricting them for on-chip GHz-range applications. Here, we demonstrate electrical synchronization of four non-vortex uniformly-magnetized STOs using a single common current source in both parallel and series configurations at 2.4 GHz band, resolving the frequency-area quandary for designing STO based on-chip communication systems. Under injection locking, synchronized STOs demonstrate an excellent time-domain stability and substantially improved phase noise performance. By integrating the electrically connected eight STOs, we demonstrate the battery-free energy-harvesting system by utilizing the wireless radio-frequency energy to power electronic devices such as LEDs. Our results highlight the significance of electrical topology (series vs. parallel) while designing an on-chip STOs system.

A Cascaded Mode-Switching Sub-Sampling PLL With Quadrature Dual-Mode Voltage Waveform-Shaping Oscillator

A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of the oscillator at 10 MHz offset are -188.2 dBc/Hz and -200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from -104.1 to -108.2 dBc/Hz at 1 MHz offset. The jitter FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</sub> is -236.2 dB.

Ultra-wideband Quadrature LC-VCO using Capacitor-Bank and backgate topology with on-chip spirally stacked inductor in 0.13 ​μm RF-CMOS process covering S–C bands

Frequency tracking and synthesizer at the mm-wave range suffer an everlasting compromise between phase noise (PN) performance and frequency tuning range (FTR) irrespective of the topology adopted. This work proposes an Ultra-Wide Band, Quadrature Voltage Controlled Oscillator (QVCO) employing an on-chip inductor and 8-Bit Capacitor-Bank (Cap-Bank) in addition to the MOS-Varactors, to bring in the best compromise between above two said constraints. The additional efforts are kept generating Quadrature operation and keeping the power dissipation in an optimized range. It is shown that unlike conventional current reuse and wider MOS topology, the proposed Cap-Bank array with scaled transistor-based switches effectively widens the tuning operation with a remarkable FTR up to 85.7%, covering the most frequently used wireless standards IEEE-802.11 a/b/g of Bluetooth and Wi-Fi in S and C bands respectively. The design has been implemented with 0.13 ​μm RF-CMOS process in ADS (Keysight Technologies). The Back-Gate topology has been used with the cross-coupled differential structure which generates the quadrature phased signals well-shaped and with the least add on power dissipation. Use of a low-loss on-chip spirally stacked inductor, enhances the chip integrity, spectrum quality and improves Phase Noise performance, providing the best phase noise of −164 dBc/Hz at 1 ​MHz (near fmax) at a power dissipation of 12 ​mW from 1.2 ​V supply. The VCO gain achieved for the entire range of 2.4–6 ​GHz, varies largely from 1332 ​MHz/V (near fmax ​= ​6 ​GHz) to 42 ​MHz/V (near fmin ​= ​2.4 ​GHz) for the coarse tuning of Cap-Bank.

A sub-harmonic injection locking clock multiplier with FLL PVT calibrator

Using the sub-harmonic injection locking technique, an enhanced differential Digitally Controlled Ring Oscillator (DCRO) with improved phase noise performance is proposed in this paper. All circuit blocks were implemented using digital design flow and designed using a hardware description language. A Frequency Locked Loop-based Process, Voltage and Temperature (PVT) calibrator was utilized to overcome PVT variations. The design was fabricated in 65 nm CMOS technology and its area is 0.017 mm2. The measured phase noise at 1 MHz offset and RMS jitter are −128 dB/Hz and 197fs, respectively. The design was tested in the presence of voltage and temperature variations. The maximum jitter difference percentage is 13.7% at 70 °C and 1.1 V and the phase noise value changes by a maximum of 0.7 dB over the whole range of voltages and temperatures. Furthermore, when the design was tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the DCRO.

Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4$\times$ Frequency Edge Combiner

In this paper, we present an all-digital ring oscillator (RO)-based Bluetooth low-energy (BLE) transmitter (TX) for ultra-low-power radios in short range Internet-of-Things (IoT) applications. The power consumption of state-of-the-art BLE TXs has been limited by the relatively power-hungry local oscillator (LO) due to the use of LC oscillators for superior phase noise (PN) performance. This paper addresses this issue by analyzing the PN limit of a BLE TX and proposes an RO-based solution for power and cost savings. The proposed transmitter features: 1) a wideband all-digital phase-locked loop (ADPLL) featuring an $f_{\mathrm {RF}} / {4}$ RO, with an embedded 5-bit TDC; 2) a 4 $\times $ frequency edge combiner to generate the 2.4-GHz signal; and 3) a switch-capacitor digital PA optimized for high efficiency at low transmit power levels. These not only help reduce the power consumption and improve PN performance but also enhance the TX efficiency for short range applications. The TX is prototyped in 40-nm CMOS, occupies an active area of 0.0166 mm2, and consumes 486 $\mu \text{W}$ in its low-power mode, while configured as a non-connectable advertiser. The TX has been validated by wirelessly communicating beacon messages to a mobile phone.

A modified multiphase oscillator with improved phase noise performance

This paper investigates the factors that influence the phase noise performance of an oscillator and proposes a modified structure for improved phase noise performance. A single and multiphase oscillator analysis using the harmonic balance method is presented. The modified structure increases the oscillation amplitude without increasing the bias current and leads to improved phase noise performance as well as decreased power consumption. The modification is analyzed and the figure of merit of the oscillator shows a significant improvement of 21dB. Numerical and analytical solutions are presented to predict the oscillation frequency and phase noise. The analytical solution is used to approximate the first harmonic and can be combined with numerical simulations to extrapolate phase noise performance.

Microwave photonic link with improved phase noise using a balanced detection scheme

A microwave photonic link (MPL) with improved phase noise performance using a dual output Mach–Zehnder modulator (DP-MZM) and balanced detection is proposed and experimentally demonstrated. The fundamental concept of the approach is based on the two complementary outputs of DP-MZM and the destructive combination of the photocurrent in balanced photodetector (BPD). Theoretical analysis is performed to numerical evaluate the additive phase noise performance and shows a good agreement with the experiment. Experimental results are presented for 4GHz, 8GHz and 12GHz transmission link and an 11dB improvement of phase noise performance at 10MHz offset is achieved compared to the conventional intensity-modulation and direct-detection (IMDD) MPL.

Phase Noise Reduction and Optimal Operating Conditions for a Pair of Synchronized Oscillators

We investigate the dynamics of a pair of noisy coupled oscillators and derive operating conditions that minimize phase noise. The generic model employed allows for general nonlinear dynamics of the resonant elements of the oscillators, in terms of their amplitude-dependent frequencies, general asymmetric coupling, and both additive and multiplicative noise sources. The model is analyzed using the method of stochastic averaging and the results suggest an optimal operating point for minimizing phase noise in either of the oscillators by varying the operating amplitudes and the nature and strength of the coupling. We also show that the system with asymmetric coupling has the ability to reduce the phase noise of the noisier oscillator beyond the expected result for synchronized oscillators. The analytical predictions, which are validated by Monte-Carlo simulations, show how one can exploit nonlinear behavior to improve phase noise characteristics using a pair of coupled oscillators. The results also point to a means of designing and optimizing larger sets of coupled oscillators to improve phase noise performance.

Robust terahertz self-heterodyne system using a phase noise compensation technique

We propose and demonstrate a robust terahertz self-heterodyne system using a phase noise compensation technique. Conventional terahertz self-heterodyne systems suffer from degraded phase noise performance due to phase noise of the laser sources. The proposed phase noise compensation technique uses an additional photodiode and a simple electric circuit to produce phase noise identical to that observed in the terahertz signal produced by the self-heterodyne system. The phase noise is subsequently subtracted from the terahertz signal produced by the self-heterodyne system using a lock-in amplifier. While the terahertz self-heterodyne system using a phase noise compensation technique offers improved phase noise performance, it also provides a reduced phase drift against ambient temperature variations. The terahertz self-heterodyne system using a phase noise compensation technique shows a phase noise of 0.67 degree in terms of a standard deviation value even without using overall delay balance control. It also shows a phase drift of as small as approximately 10 degrees in an open-to-air measurement condition without any strict temperature control.

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and $\Delta \Sigma $ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of $-$ 104 dBc/Hz and 1.5 ps $_{\rm rms}$ integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of $-$ 225.8 dB.

A Harmonic Class-C CMOS VCO-Based on Low Frequency Feedback Loop: Theoretical Analysis and Experimental Results

A novel harmonic Class-C CMOS VCO architecture with improved phase noise performance and power efficiency is presented in this paper. The VCO is based on the widely adopted topology consisting in a crossed pair of NMOS devices refilling a symmetric resonator with a center tapered inductor and biased by a top PMOS current generator. The Class-C operation mode is obtained through a low frequency feedback loop constituted by an operational transconductance amplifier operating the difference between the inductor center tap voltage and a reference voltage, pushing gate polarization voltage of VCO crossed pair devices well below their threshold voltage. The Class-C VCO achieves a theoretical 2.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator for the same current consumption. A prototype of the VCO is implemented in a standard RF 55 nm CMOS technology and compared to both a standard and an optimized VCO implemented in the same technology. All these VCOs share a copy of a unique resonator. The Class-C VCO is tunable over the frequency band 6.5-7.8 GHz and displaying an average phase noise lower than -127 dBc/Hz @ 1 MHz offset with a power consumption of 18 mW, for a state-of-the-art figure-of-merit of -187 dBc/Hz @ 1 MHz and -191 dBc/Hz @ 10 MHz offsets, respectively.

Improved configuration and reduction of phase noise in a narrow linewidth ultrawideband optical RF source.

In this Letter, we report on the improved configuration of a widely tunable optical RF generation system, particularly for the generation of low-frequency RF, as well as the reduction of phase noise in that same system. Using an amplitude modulator, a simplified system design was demonstrated with fewer components and improved phase noise performance, especially at RF frequencies below ∼36 GHz. Excess phase noise due to acoustic vibrations of the optical fibers was also successfully eliminated by mechanical isolation. A minimum phase noise of -124 dBc/Hz at 10 kHz offset was demonstrated at 4 GHz.

Design of a Low Phase Noise VCO for WSN Applications

A fully integrated LC VCO with 1V low voltage supply, applied in the frequency synthesizer for wireless sensor network applications, is designed and implemented in TSMC 0.18μm RF/MS CMOS process with low power consumption and good phase noise performance. To conquer the problems brought by low voltage, the structure of VCO is carefully selected. A 4 bit switched capacitor array is used to widen tuning range without worsen the phase noise performance. Besides, a 2 bit switched tail current source array is used to achieve power consumption adapted to the desired operating scenario. Second harmonic filter technology is taken to improve phase noise performance. The VCO designed in this paper has good phase noise performance and low power consumption by optimization. The chip size is 860μm×730μm. Post-simulation results show that the frequency range is between 4.57~6.18GHz with tuning range 30%, the center frequency is 5.375GHz, and the power consumption of VCO core is between 2.6~4mW. At the meanwhile, phase noise is between-116.0~ -117.8dBc@1.0MHz.

Low power low phase noise phase locked loop frequency synthesizer with fast locking mode for 2.4 GHz applications

We designed a low power low phase noise phase locked loop (PLL) frequency synthesizer for 2.4 GHz wireless communication applications. Current reusing technique and triple-well NMOS transistors are applied to reduce power consumption and improve phase noise performance of the voltage controlled oscillator (VCO), respectively. The synthesizer has a fast locking mode that uses frequency presetting technique to greatly shorten the locking time. The synthesizer was implemented in 0.18 µm CMOS process. The chip core area is 1.49 mm2. Measured results show that the output frequency tuning range is 2.16–2.55 GHz. The phase noise is −124.18 dBc/Hz at 1 MHz from a 2.4 GHz carrier. The power consumption is 4.98 mW and the locking time in fast locking mode is about 4 µs.

A Class-F CMOS Oscillator

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of -136 dBc/Hz at 3 MHz offset from the carrier over 5.9-7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while drawing 12 mA from 1.25 V supply.

Techniques of Power Phase-Noise Optimization of 2.4 / 4.8 GHz CMOS VCO with Switched Capacitor Array Using Bondwire Inductor

This paper presents theoretical analysis of the maximum operating frequency of proposed Source Degeneration (SD) and Conventional CML D-Latch are estimated. The approach is based on the voltage transfer function, which is derived from small signal model of the circuit. Design approach with pre and post layout simulation results have been presented in detail and compared the performance in terms of power consumption, self oscillation frequency, sensitivity and supply voltage. With example shows the, all pMOS Voltage Controlled Oscilaator (VCO) with MOS capacitor switched capacitor array (SCA) generates the high frequency sinewave reference signals fed in to both divider for to get quadrature (Q) sinewave signals. Off Chip Bondwire inductor is used instead of on chip spiral inductor in all-pMOS VCO as it have high quality factor. Also, it will neglect the variations of carrier frequency and it gives additional performance like phase noise, power consumption, area than using spiral inductor. Even if use spiral inductor in all-pMOS VCO, Bondwire inductor also presents due to low impedance path between drain and ground terminal. Various optimization techniques are implemented while designing a QVCO, which facilitates is used to achieve a low power low phase noise performance. Compared to other types of QVCO, the conventional QVCO shows good phase noise performance than normally achieved 6 dB phase noise improvement with carrier frequency. The simulated results shows about 5 dB, 4 dB, 4 dB and 4 dB of phase noise improvement at 10 kHz, 100 kHz, 1 MHz and 3 MHz offset frequency from the 2.4 GHz carrier frequency. This combinational topology doesn't consume additional power and area than others and shows with improved phase noise performance. The pre and post layout simulation results are compared of both proposed (SD) and conventional QVCO, which is designed in 180 nm CMOS technology as 1V.

A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

A low power low phase noise frequency synthesizer with subharmonic injection locking is proposed for ZigBee applications. The PLL is based on a ring VCO to decrease area and production cost. In order to improve phase noise performance, a high frequency injection signal of which frequency varies with channel number is used. The circuit is designed in TSMC 0.18 μm CMOS technology and simulated in ADS (Advanced Design System). The phase noise at 3.5 and 10 MHz offsets is -116 and -118 dBc/Hz, respectively, and total circuit consumes 2.2 mA current.

A ROBUST 900 MHz RFID READER CHIP WITH RC-CALIBRATION

A fully integrated RFID reader chip targeted to operate in the frequency range of 860 MHz to 960 MHz is designed, simulated and fabricated. To reduce the chip performance degradation due to process and temperature variation, resistor and capacitor calibration is adopted. The output codes of resistor calibration are used to adjust main circuit blocks' biasing current while the output codes of capacitor calibration are used to fine tune filter bandwidth and Digital-to-analog converter (DAC) conversion accuracy. Dual-tuned magnetic coupled LC tanks are also introduced in our VCO design to improve phase noise performance and extend tuning range, so as to enhance the robustness of the proposed RFID reader system. The reader is implemented with a low cost 90 nm standard CMOS process and has a chip area of 3.1 mm by 3.3 mm. The chip is packaged with QFN48 and tested on PCB. The proposed RFID reader consumes 90 mW of power and has robust performance against temperature, voltage supply and process variation. The merits of the chip make it ideal for various application scenarios.