Abstract
A low power low phase noise frequency synthesizer with subharmonic injection locking is proposed for ZigBee applications. The PLL is based on a ring VCO to decrease area and production cost. In order to improve phase noise performance, a high frequency injection signal of which frequency varies with channel number is used. The circuit is designed in TSMC 0.18 μm CMOS technology and simulated in ADS (Advanced Design System). The phase noise at 3.5 and 10 MHz offsets is -116 and -118 dBc/Hz, respectively, and total circuit consumes 2.2 mA current.
Highlights
The necessity for mobile computing and networking has led to the development of various wireless standards over the last decade
It is very difficult to reduce the scale of RF/analog circuit blocks, such as voltage-controlled oscillators (VCOs), phase-locked loops (PLLs) and power amplifiers, because of the presence of inductors that does not scale with advancements in technology [2]
This paper presents a frequency synthesizer for ZigBee applications
Summary
The necessity for mobile computing and networking has led to the development of various wireless standards over the last decade One of these standards is IEEE 802.15.4/ ZigBee that has been recently developed to provide the needs of low power, low data rate, low production cost, and short range wireless networks. To cater this need, great efforts are made to develop those systems using highly scaled advanced CMOS processes. If there is a method that can alleviate the poor phase noise problem, the ring VCOs can be introduced as a good option for many applications One of these ways is using injection locking technique [3].
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
