Implementation Of Logic Gates Research Articles

Ultra Low Power Consumption Optoelectronic Logic Operation of CuO/BaTiO3 Heterojunction Photodetector with Tunable Internal Electric Field Based on Poling Effect

AbstractThe study presents a novel self‐powered ultraviolet (UV) photodetector harnessing both polarization fields and photovoltaic effects, enabling the realization of ultra‐low power, reconfigurable optoelectronic logic gates. The approach is demonstrated on a CuO/BaTiO3 heterojunction photodetector. The behavior of the photodetector is augmented by the poling effect, aligning the internal electric field of the BaTiO3 through the application of a robust external electric field, thereby facilitating the implementation of optoelectronic logic gates. In the unpoled state, the “XOR” and “OR” logic gates operated at voltages of 750 and −500 µV, respectively. However, upon poling up state, the “XOR” logic gate exhibits reduced operation voltage, operating at 500 µV, while the “OR” logic gate implements clarity at −500 µV. In the unpoled state the “AND” logic gate does not operate; however, upon poling in the downward direction, it operated at −500 µV. The achievement demonstrates successful ultra‐low‐power logic operations, utilizing voltages in the hundreds of micron scale, under a 310 nm wavelength and a light intensity of 0.52 mW·cm−2. Furthermore, controllable polarization electric fields in BaTiO3 enable the operation of “AND” logic gate in the unpoled state, presenting a promising avenue for future research in optoelectronic logic gate design.

Computation Implemented by the Interaction of Chemical Reaction, Clustering, and De-Clustering of Molecules.

A chemical reaction and its reaction environment are intrinsically linked, especially within the confines of narrow cellular spaces. Traditional models of chemical reactions often use differential equations with concentration as the primary variable, neglecting the density heterogeneity in the solution and the interaction between the reaction and its environment. We model the interaction between a chemical reaction and its environment within a geometrically confined space, such as inside a cell, by representing the environment through the size of molecular clusters. In the absence of fluctuations, the interplay between cluster size changes and the activation and inactivation of molecules induces oscillations. However, in unstable environments, the system reaches a fluctuating steady state. When an enzyme is introduced to this steady state, oscillations akin to action potential spike trains emerge. We examine the behavior of these spike trains and demonstrate that they can be used to implement logic gates. We discuss the oscillations and computations that arise from the interaction between a chemical reaction and its environment, exploring their potential for contributing to chemical intelligence.

Protecting coherence from the environment via Stark many-body localization in a Quantum-Dot Simulator

Semiconductor platforms are emerging as a promising architecture for storing and processing quantum information, e.g., in quantum dot spin qubits. However, charge noise coming from interactions between the electrons is a major limiting factor, along with the scalability of many qubits, for a quantum computer. We show that a magnetic field gradient can be implemented in a semiconductor quantum dot array to induce a local quantum coherent dynamical ℓ−bit exhibiting the potential to be used as logical qubits. These dynamical ℓ−bits are responsible for the model being many-body localized. We show that these dynamical ℓ−bits and the corresponding many-body localization are protected from all noises, including phonons, for sufficiently long times if electron-phonon interaction is not non-local. We further show the implementation of thermalization-based self-correcting logical gates. This thermalization-based error correction goes beyond the standard paradigm of decoherence-free and noiseless subsystems. Our work thus opens a new venue for passive quantum error correction in semiconductor-based quantum computers.

Fault-Tolerant Code-Switching Protocols for Near-Term Quantum Processors

Topological color codes are widely acknowledged as promising candidates for fault-tolerant quantum computing. Neither a two-dimensional nor a three-dimensional topology, however, can provide a universal gate set {, , }, with the gate missing in the two-dimensional and the gate in the three-dimensional case. These complementary shortcomings of the isolated topologies may be overcome in a combined approach, by switching between a two- and a three-dimensional code while maintaining the logical state. In this work, we construct resource-optimized deterministic and nondeterministic code-switching protocols for two- and three-dimensional distance-three color codes using fault-tolerant quantum circuits based on flag qubits. Deterministic protocols allow for the fault-tolerant implementation of logical gates on an encoded quantum state, while nondeterministic protocols may be used for the fault-tolerant preparation of magic states. Taking the error rates of state-of-the-art trapped-ion quantum processors as a reference, we find a logical failure probability of 3% for deterministic logical gates, which cannot be realized transversally in the respective code. By replacing the three-dimensional distance-three color code in the protocol for magic state preparation with the morphed code introduced in Vasmer and Kubica [PRX Quantum 3, 030319 (2022)], we reduce the logical failure rates by 2 orders of magnitude, thus rendering it a viable method for magic state preparation on near-term quantum processors. Our results demonstrate that code switching enables the fault-tolerant and deterministic implementation of a universal gate set under realistic conditions, and thereby provide a practical avenue to advance universal, fault-tolerant quantum computing and enable quantum algorithms on first, error-corrected logical qubits. Published by the American Physical Society 2024

A low-latency and energy-efficient 4-bit absolute value detector for brain-machine interface applications

This research article aims to develop a 4-bit absolute value detector, balancing speed and power efficiency, with potential applications in Brain-Machine Interface (BMI) systems. The detector outputs a binary signal, indicating whether the absolute value of the input surpasses a predefined threshold. The design integrates two primary modules: an absolute value calculator and a comparator. Initially, the study focuses on enhancing the architecture of a multiplexer-based adder for absolute value calculation and selecting an efficient comparator structure, emphasizing least significant bit comparison. Further, the implementation of logic gates using Complementary Metal-Oxide-Semiconductor (CMOS) technology is elaborated. The research concludes by assessing the minimum delay achievable in the critical path, quantified at 74.22 units, and investigating strategies to minimize energy consumption. This is achieved by adjusting gate dimensions and supply voltage, aiming for a delay 1.5 times the minimum. The energy expenditure of the critical path is extrapolated to estimate the overall circuit consumption. The findings demonstrate that, at 1.5 times the minimal delay, the circuit achieves a maximum energy savings of 62.8% with a supply voltage of 0.815V.

Design and implementation of the logic gates using electrically doped configurable polarity control double gate tunnel FET

This paper designs and implements the basic logic and universal gates based on the proposed electrically doped, configurable polarity control double gate tunnel FET (ED-CPC-DGTFET). In contrast to the CMOS and MOSFET, the primary concern of the proposed device is to overcome the transistor count needed to design logic gates. A few compact realizations of logic gates have been reported earlier using conventional double-gate TFETs. The main key to designing and implementing logic gates with the proposed structure is controlling the channel’s tunneling barrier height by altering the gate electrode work function. Additionally, abrupt interband tunneling of TFET by varying gate bias makes the device appropriate for implementing logic gates. The proposed device has a dynamic configuration that can change from n-type to p-type DGTFET by varying the bias at PG-1 and PG-2. Since lightly doped TFETs have a low ON-state current therefore, a high-k material (HfO 2 ) is employed in place of SiO 2 on top of the source side to enhance the ON-state current. Using two-dimensional simulations, the device is designed to implement logic gates with gate lengths of 50 nm and silicon body thicknesses of 10 nm (t si ). OR and AND logic gates are implemented using the n-type ED-CPC-DGTFET structure, and universal gates are implemented using the p-type variant of the proposed ED-CPC-DGTFET structure by independently biasing the top and bottom gates against various inputs.

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Beyond Silicon: The Advent of Biomolecular Computing

ABSTRACT: Bio computing is an emerging interdisciplinary field that harnesses the information processing capabilities of biological substrates like DNA, proteins and cells to perform computational tasks. Rather than relying solely on conventional silicon-based computers, bio computing leverages the innate computational properties of biomolecules to encode, store, process and transmit information in unconventional ways. Core approaches include DNA computing, which uses DNA biochemistry to solve problems in a massively parallel fashion. Protein computing utilizes protein conformational dynamics to implement logic gates and communication modules for molecular information processing. Cellular computing focuses on engineering gene circuits and synthetic biology tools to program computational behaviours in living cells. Neural computing builds artificial neural networks inspired by biological brains. Key application areas include biomedicine, smart drug delivery systems, biosensing, hybrid organic-inorganic electronics, and biomolecular manufacturing. While still facing challenges around biocompatibility, programming complexity and ethical concerns, bio computing has achieved major technical milestones demonstrating its promise. Continued progress at the interface of biology and computing could enable future technologies like bio processors, in-vivo biocomputers, living materials and bio-intelligent systems. With responsible development, bio-inspired computation may catalyse the next revolution in human technological capabilities. This emerging field thus warrants enthusiastic attention as computation further converges with the living world.

Azaindole based fluorescent chemosensors for detecting Fe(II/III) ions and molecular logic gate implementation

A series of tridentate polypyridyl N^N^N/N^C^N-coordinating ligands (R1, L1, L2) were synthesized by copper-catalyzed Ullmann coupling (C–N bond-forming) reaction in moderate yields (∼50 %). Two charged ligands, L3 and L4 were also synthesized by methylation of L1 and L2 in moderate yields (∼45 %). These ligands were characterized by a set of analytical techniques including NMR, HRMS and single-crystal XRD. The electrochemical and photophysical properties of these ligands were examined using cyclic voltammetry, UV–vis absorption and luminescence spectroscopies. Theoretical calculations in the level of DFT and TD-DFT were also performed for the detailed studies of the optoelectronic properties of these compounds. These ligands displayed either an admixture of singlet ligand-centered (1LC) and singlet charge-transfer (1CT) transitions or pure 1LC/1CT luminescence in some cases. Ligands R1 and L1 which were highly emissive were further used as selective chemosensors for the detection of Fe(II)/(III) with a “turn-off” fluorescence behavior in a binding stoichiometry of 2:1 = ligand: M(II/III) [M = Fe(II)/Fe(III)] and a limit of detection up to 0.87–1.19 ppm level. L1 was also realized for the successful construction of the molecular logic gate.

Implementation of Logic Gates Using Drain Engineering Dual Metal Gate-Based Charge Plasma TFET (DE-DMG-CP-TFET)

For digital applications, researchers are exploring the use of Tunnel Field-Effect Transistors (TFETs) as an alternative to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). TFETs offer unique qualities that can be harnessed in digital applications. The presented work focuses on the Drain Engineering Dual Metal Gate based Charge Plasma TFET (DE-DMG-CP-TFET) and its ability to implement various logic functions utilizing 2D device simulations. This simulation refers to employing computational tools to analyze electronic devices in two spatial dimensions, considering parameters such as current-voltage characteristics, electric field analysis, and energy band diagrams. This simulation-based approach enables a comprehensive understanding of the device’s operation under different conditions and facilitates the optimization of its performance. The simulations provide insights into the impact of design parameters, material properties, and device configurations on its functionality. By leveraging the ambipolar nature and gate-controlled tunneling capability of TFETs, compact logic functions can be realized by carefully designing the gate-source overlap and selecting an appropriate silicon body thickness. This research highlights the potential of TFETs in compact logic implementation and demonstrates the value of two-dimensional device simulations in understanding device behavior and optimizing performance. It is demonstrated that by biasing the two gates individually, a single DE-DMG-CP-TFET may implement logic operations like OR, AND, NAND and NOR. Using a gate-source overlap (LOV) and picking the right silicon body thickness are crucial for obtaining distinct logic functions from a DE-DMG-CP-TFET.

Contributions of Light to Novel Logic Concepts Using Optoelectronic Materials.

Instead of the current method of transmitting voltage or current signals in electronic circuit operation, light offers an alternative to conventional logic, allowing for the implementation of new logic concepts through interaction with light. This manuscript examines the use of light in implementing new logic concepts as an alternative to traditional logic circuits and as a future technology. This article provides an overview of how to implement logic operations using light rather than voltage or current signals using optoelectronic materials such as 2D materials, metal-oxides, carbon structures, polymers, small molecules, and perovskites. This review covers the various technologies and applications of using light to dope devices, implement logic gates, control logic circuits, and generate light as an output signal. Recent research on logic and the use of light to implement new functions is summarized. This review also highlights the potential of optoelectronic logic for future technological advancements.

Implementation of Digital Circuits using the Internet of Things

Digital circuits are used everywhere in day to day lives. There is a need to learn it practically by every undergraduate in laboratories. Digital trainer kits are being used in laboratories which use a basic circuit connection approach. Only this approach is not sufficient for a student to explore deep enough because digital circuits can be implemented by any number of approaches. A smart approach is required for enhancement of the trainer kit. This project incorporates the Iot approach required for implementation of digital circuits. This project works as a digital demo kit which helps students to smartly learn boolean functions with the Iot approach. Arduino microcontroller is a substitute for digital circuits and it brings smartness and digital logic in one platform to easily achieve the required digital functionality. In this project, implementation of logic gates, basic combinational and sequential circuits will be done. This project uses Arduino programming which is executed with respect to digital circuits. The inputs are given using ultrasonic sensors, input parameters are given efficiently using the bluetooth module and the outputs will be shown on a two bit seven segment display. Trainer kits can be fabricated using this mechanism and components and thus, it would definitely find a good application in laboratories helping undergraduates to learn in a better manner.

Photopatternable High‐k Polysilsesquioxane Dielectrics for Organic Integrated Devices: Effects of UV Curing on Chemical and Electrical Properties (Adv. Funct. Mater. 19/2023)

Polysilsesquioxanes In article number 2214865, Insik In, Yong Jin Jeong, Se Hyun Kim, and co-workers prepare two types of UV-curable high-dielectric-constant polysilsesquioxanes by introducing epoxy-containing side chains: 1) glycidyl epoxy-containing linear groups and 2) bulky cycloaliphatic epoxy-containing groups. The structure of the side chains influenced the UV curing behavior and capacitance characteristics of polysilsesquioxanes. These polysilsesquioxanes are used to implement logic gates and memory cells exhibiting low-voltage and non-destructive operations.

Principles of Logic Design with Nanoscale Thin Film Memristive Systems for High Performance Digital Circuit Applications

The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a variety of materials. This paper aims to examine the principles of logic design using such two terminal memristive systems for high performance digital circuit applications. As against logic design with standard CMOS, the benefits of logic design with memristors have been stated. The realization and operation of memristor based AND and OR hybrid logic gates obtained by integrating memristors with standard CMOS logic have been discussed. The IMPLY and MAGIC logic families have been demonstrated by covering MAGIC NOR and NAND logic gate implementation with MAGIC NOR in detail. A qualitative comparison has been drawn towards the end of the paper to conclude on the suitability and application space for each of the logic families studied in this paper. This work also describes the hybrid CMOS-memristive logic family known as MRL (Memristor Ratioed Logic). With the addition of CMOS inverters, this logic family's OR and AND logic gates, which are based on memristive components, are given a full logic structure and signal restoration. The MRL family, in contrast to earlier memristor-based logic families, is compatible with conventional CMOS logic.

Design and Construction of a Digital Logic Training Module for Laboratory Experimentation

A Digital Logic Trainer is used to train students on experimental verification and implementation of basic logic gates. This research work describes a digital logic training (DLT) module designed and constructed using semiconductor components such as diodes, transistors, and integrated circuits. The DLT module can be used to verify logic gate theorems including Boolean expressions, combinational logic designs and Karnaugh’s reduction techniques for a given logic circuit. The front panel of the DLT module comprises of different Boolean symbols for easy logic gates identification and operates effectively on a 5 V DC rectified from a 220 V AC power supply. The DLT module performs favourably well when compared with commercially available types and comes at a lower production cost.

All-optical XOR and NXOR logic gate implementation method based on dual-parallel phase modulators

We proposed a new and simple scheme to implement exclusive OR (XOR) and not exclusive OR (NXOR) logic operations in the optical domain enabled by a dual-parallel phase modulator (PM). Both the intensity and phase of the optical signal are utilized to represent the four different states of two binary inputs, and direct detection is used to map the four states to the corresponding binary output. Through numerical analysis, two PMs with phase offsets were adjusted to π / 2, and the phase shifter between the two PMs was controlled atπ / 2; thus, the NXOR logic gate was successfully carried out. Two PMs with phase offsets were adjusted to π / 2, and the phase shifter between the two PMs was controlled atπ; thus, the XOR logic gate was successfully carried out. Simulations were successfully carried out at the speed of 10 Gb/s.

Numerical and Experimental Data of the Implementation of Logic Gates in an Erbium-Doped Fiber Laser (EDFL)

In this article, the methods for obtaining time series from an erbium-doped fiber laser (EDFL) and its numerical simulation are described. In addition, the nature of the obtained files, the meaning of the changing file names, and the ways of accessing these files are described in detail. The response of the laser emission is controlled by the intensity of a digital signal added to the modulation, which allows for various logical operations. The numerical results are in good agreement with experimental observations. The authors provide all of the time series from an experimental implementation where various logic gates are obtained.

Implementation of Logic Gates in an Erbium-Doped Fiber Laser (EDFL): Numerical and Experimental Analysis

At a time when miniaturization and optimization of resources are in the foreground, the development of devices that can perform various functions is a primary goal of technological development. In this work, the use of an Erbium-Doped Fiber Laser (EDFL) is proposed as a basic system for the generation of an optical logic gate. Taking advantage of the dynamic richness of this type of laser and its use in telecommunication systems, the dynamic response is analyzed when the system is perturbed by a digital signal. The emission response of the system is controlled by the intensity of the digital signal, so that it is possible to obtain different logic operations. The numerical results are in good agreement with the experimental observations. The presented work raises new aspects in the use of chaotic systems as a means of obtaining optical logic gates.

Multiqudit interactions in molecular spins

We study photon-mediated interactions between molecular spin qudits in the dispersive regime of operation. We derive from a microscopic model the effective interaction between molecular spins, including their crystal field anisotropy (i.e., the presence of non-linear spin terms) and their multi-level structure. Finally, we calculate the long time dynamics for a pair of interacting molecular spins using the method of multiple scales analysis. This allows to find the set of 2-qudit gates that can be realized for a specific choice of molecular spins and to determine the time required for their implementation. Our results are relevant for the implementation of logical gates in general systems of qudits with unequally spaced levels or to determine an adequate computational subspace to encode and process the information.

Information Processing Using Networks of Chemical Oscillators.

I believe the computing potential of systems with chemical reactions has not yet been fully explored. The most common approach to chemical computing is based on implementation of logic gates. However, it does not seem practical because the lifetime of such gates is short, and communication between gates requires precise adjustment. The maximum computational efficiency of a chemical medium is achieved if the information is processed in parallel by different parts of it. In this paper, I review the idea of computing with coupled chemical oscillators and give arguments for the efficiency of such an approach. I discuss how to input information and how to read out the result of network computation. I describe the idea of top-down optimization of computing networks. As an example, I consider a small network of three coupled chemical oscillators designed to differentiate the white from the red points of the Japanese flag. My results are based on computer simulations with the standard two-variable Oregonator model of the oscillatory Belousov–Zhabotinsky reaction. An optimized network of three interacting oscillators can recognize the color of a randomly selected point with >98% accuracy. The presented ideas can be helpful for the experimental realization of fully functional chemical computing networks.