Digital Signal Processor Implementation Research Articles

Implementation of Digital Signal Processor for Pulse Doppler Radar

This paper presents the design and implementation of a digital signal processor (DSP) board, utilizing a TMS320C50 family DSP chip, for pulse-Doppler radar systems. Pulse-Doppler radar systems often encounter challenges such as strong clutter, noise, and jamming in dealing with echoes. To overcome these challenges, advanced digital signal processing techniques are employed. The main objective of this paper is to introduce a cost-effective signal processing solution that significantly enhances the performance of the radar system and brings it up to speed with modern radar technologies. The hardware described in this work can also be effectively utilized for implementing various types of signal processing algorithms. Additionally, as a secondary objective, the paper presents the digital realization of a radar detector. Traditionally, this detector was constructed using an analog Doppler filter bank. However, in this work, it is digitally implemented using N digital filters in place of the analog bank. By utilizing the designed DSP board and implementing the radar detector digitally, this paper demonstrates the potential for improved performance and efficiency in pulse-Doppler radar systems. The advancements made in this work contribute to the development of cost-effective and technologically advanced radar systems. The research results are presented for four different wind conditions, showcasing the effectiveness of the proposed approach. Furthermore, the paper suggests an algorithm that combines parametric and non-parametric techniques and provides a detailed explanation of its implementation. Finally, using the non-parametric technique, the probability of detection curves (PD) are simulated with respect to the signal-to-clutter ratio (SCR) for each wind condition, and the simulation results are depicted and compared. The achievements of this paper include the proposal of an efficient approach for clutter suppression in ground surveillance pulse Doppler radar, the comparison of different clutter suppression algorithms, and the development of an algorithm that combines parametric and non-parametric techniques. The simulation results provide valuable insights into the performance of the proposed algorithms under different wind conditions.

Application of two-dimensional chaotic system and implementation of DSP

Abstract Given that the limited complexity of most current 2D maps undermines chaos-based practical applications, this paper proposes a 2D Logical Cosine Coupled Map (2D-LSCCM) and compares the bifurcation maps, Lyapunov exponent spectrum, and spectral entropy complexity of the classical 2D chaos model. Based on this model, this paper proposes an image encryption scheme using ascending alignment permutation and XOR pixel diffusion algorithm. After a series of tests, such as chi-square test, anti-attack test, key sensitivity test, and correlation test, the simulation findings show that the chaotic system proposed in this paper has excellent security performance compared with other systems. Moreover, a hardware platform based on DSP (Digital Signal Processing) and NIST test have been developed to analyze and test chaotic sequences.

A Study on the Distributed-Control Architecture of a DSP-Based Solid-State Transformer System with Implementation

This article proposes a Distributed-control Architecture (D-CA) and an operation sequence with start-up strategies for a Digital Signal Processor (DSP)-based Solid-State Transformer (SST). Although various control techniques for SSTs have been reported in earlier studies, there is still a lack of research covering comprehensive content, including hierarchical control architectures and operation sequences with start-ups considering the implementation of DSPs. Therefore, this article addresses the following factors of SST. First, the D-CA is described for the design of the hierarchy between control boards. With the D-CA, because sub-boards are in charge of their corresponding DC-link voltage balancing control individually, the computational burden on the master board can be reduced. Second, the operation sequence of the SST system is explained based on the SST with D-CA. The step of DC-link voltage balance is considered throughout the entire operation sequence for safe driving. Furthermore, the PWM start-up strategies for a Cascade H-bridge Multilevel (CHM) converter and Dual Active Bridge (DAB) converter are proposed to prevent switching pulse errors caused by DSP operating characteristics. These start-up strategies reduce the current surges. The validity of the proposed D-CA and operation sequence with start-up strategies are verified by experimental results.

Complex Dynamical Characteristics of the Fractional-Order Cellular Neural Network and Its DSP Implementation

A new fractional-order cellular neural network (CNN) system is solved using the Adomian decomposition method (ADM) with the hyperbolic tangent activation function in this paper. The equilibrium point is analyzed in this CNN system. The dynamical behaviors are studied as well, using a phase diagram, bifurcation diagram, Lyapunov Exponent spectrum (LEs), and spectral entropy (SE) complexity algorithm. Changing the template parameters and the order values has an impact on the dynamical behaviors. The results indicate that rich dynamical properties exist in the system, such as hyperchaotic attractors, chaotic attractors, asymptotic periodic loops, complex coexisting attractors, and interesting state transition phenomena. In addition, the digital circuit implementation of this fractional-order CNN system is completed on a digital signal processing (DSP) platform, which proves the accuracy of ADM and the physical feasibility of the CNN system. The study in this paper offers a fundamental theory for the fractional-order CNN system as it applies to secure communication and image encryption.

Design and DSP implementation in HIL of nonlinear observers for a doubly fed induction aero-generator

This paper reports on the conception and digital signal processor (DSP)-based hardware-in-the-loop realisation of a nonlinear observer for a grid-connected variable speed wind turbine using a doubly fed induction generator (DFIG). The objective of this work is to build some observation structure based on the extended Kalman filter (EKF), the sliding mode observer (SMO) and the adaptive model reference adaptive system (MRAS) observer to observe certain quantities of the wind power system connected to the electrical grid in order to reduce the complexity and the cost of the hardware, to achieve an increased mechanical robustness, to operate in hostile environments, to have a higher reliability and to ensure an unchanged inertia of the system. The proposed observers will be combined with robust nonlinear controls based on the backstepping approach to control the wind energy conversion system (WECS). The whole will be implemented on a TMS320F28335 DSP board. A comparative analysis of the proposed observers will be carried out. Through the results of the DSP implementation in hardware in the loop (HIL), we will prove that this improved combination increases the desired performance.

Integer Based Fully Homomorphic DSP Accelerator using Weighted-Number Theoretic Transform

Fully Homomorphic Encryption (FHE) has gained wide attention in cloud security as it allows computation on encrypted data. However, it requires a huge key size, resulting in impractical execution time. In this paper, we proposed an FHE hardware accelerator employing Weighted-Number Theoretic Transform (NTT) multiplier. NTT parameters are selected, in a way that the proposed design is executable on Digital Signal Processing (DSP) multiplier, to exploit its high clock rate. As the NTT kernel, is in general form, it can be pre-computed and stored in Look-up Tables (LUTs). The same LUTs are also usable for weight-factor as they both have symmetric periodicity properties. This optimization has saved 70% of LUTs utilization. Next optimization is proposed on reduction within NTT. The special prime moduli are exploited to accomplish a simple operation, where inverse Montgomery multiplication is replaced with shift and subtraction. The proposed optimizations are implemented for FHE encryption and realized on Kintex 7 platform. A magnitude of 93.2% speedup improvement is achieved for Toy, compared to benchmark software implementation. As the proposed design is targeted for full DSP implementation, it achieved a higher clock frequency (249.19 MHz), while consuming lower hardware resources.

A High-Accuracy Single-Photon Time-Interval Measurement in Mega-Hz Detection Rates With Collaborative Variance Reduction: Theoretical Analysis and Realization Methodology

An almost all-digital time-to-digital converter possessing sub-picosecond resolution, scalable dynamic range, calibratable linearity, high noise-immunity, and fast conversion-rates can be achieved by a stochastic random sampling-and-averaging approach with the proposed collaborative variance reduction (VR) technique for a wide range of time-correlated single-photon counting applications. This paper presents detailed theoretical analysis and behavior-model verifications of both self-antithetic and control-variate VR techniques to enhance the conversion-rate of an asynchronous RSA-based TDC up to 1.5 MHz with 12-ENOB accuracy, 0.36-pJ/step energy efficiency, and 23% power overhead. Also, the conversions of the mathematical closed-form expressions into digital signal-processing implementations are derived and demonstrated for the forthcoming silicon-photonics integrated-circuit realization.

Real-time digital signal processing implementation for in-beam PET of radiotherapy imaging in HIMM

The in-beam positron emission tomography (ibPET) is dedicated to radiotherapy imaging of the heavy-ion medical machine (HIMM), which requires precise online measurement, as well as real-time signal processing capability of the electronics. In this paper, we present the implementation of real-time digital signal processing in the data acquisition unit (DAQU) for an ibPET system based on the photomultiplier tube (PMT) readout of lutetium-yttrium oxyorthosilicate (LYSO) scintillator crystals. We have designed 10-channel customized signal processing circuit on a high-performance FPGA, which supports 3 working modes (single event processing mode, self-calibration mode and raw ADC data mode), position calculation, crystal locating, event sorting, and etc. Moreover, the implementation of real-time corrections is capable of dealing with photon peak correction to 511 keV and crystal ID-based time correction. The implemented real-time ibPET system can achieve 46% data compression and beyond 1,000,000 events/sec/channel signal processing capabilities. A series of initial tests is conducted, and the results indicate that this design meets the application requirement on online processing.

Single photon imaging with multi-scale time resolution

To avoid echo photons to be submerged in noise in rough terrain or dynamic applications, a single photon imaging mechanism with multi-scale time resolution is proposed in this paper. Combining with adaptively thresholding technique, multiple histograms with different time resolutions are produced to cluster the echo photons into a time bin and then separate them from the noise. With microsecond-scale resolution, uncertainty in the position of an object can be reduced from several kilometers to 300 meters, and therefore the computational overheads are saved by only investigating depths with picosecond-scale resolution where an object is present. Reconstructed results of the two near surfaces show that the depth accuracy is less than 0.15 m in the conditions of 8 echo photons and 1 Mcps background count rate, even though the pulse width of laser source reaches 3.5 ns (equivalent to an uncertainty of 0.525 m). In addition, the echo can be distinguished from the noise clearly when the background count rate varies from 200 kcps to 1 Mcps. The proposed method is suitable for implementation in digital signal processor (DSP) due to low data volumes and computational overheads.

Matched Filtering for MIMO Coherent Optical Communications with Mode-Dependent Loss Channels.

The use of digital signal processors (DSP) to equalize coherent optical communication systems based on spatial division multiplexing (SDM) techniques is widespread in current optical receivers. However, most of DSP implementation approaches found in the literature assume a negligible mode-dependent loss (MDL). This paper is focused on the linear multiple-input multiple-output (MIMO) receiver designed to optimize the minimum mean square error (MMSE) for a coherent SDM optical communication system, without previous assumptions on receiver oversampling or analog front-end realizations. The influence of the roll-off factor of a generic pulse-amplitude modulation (PAM) transmitter on system performance is studied as well. As a main result of the proposed approach, the ability of a simple match filter (MF) based MIMO receiver to completely eliminate inter-symbol interference (ISI) and crosstalk for SDM systems under the assumption of negligible MDL is demonstrated. The performance of the linear MIMO fractionally-spaced equalizer (FSE) receiver for an SDM system with a MDL-impaired channel is then evaluated by numerical simulations using novel system performance indicators, in the form of signal to noise and distortion ratio (SNDR) loss, with respect to the case without MDL. System performance improvements by increasing the transmitter roll-off factor are also quantified.

Bayesian Processors of Radar Signals for the Skyguard Radar System of the Ecuadorian Army

This paper talks about the implementation of an advanced Bayesian digital signal processor applied on the Skyguard Ecuadorians army radar. This new auto-regressive processor uses adaptive filters for clutter cancelation, allowing its implementation in general purpose hardware. The proposed processor is tested both in a simulated environment and using real signals obtained from the Skyguard Radar. Using a signal-to-clutter rate lower than 0 dB with a probability of detection higher than 90% the Receiver Operating characteristic Curves for Moving Target Indication, Moving Target Detection and the processor proposed here were obtained. The proposed auto-regressive processor presents a gain of 13 dB compared to the Moving Target Indication processor, and a performance similar to the Moving Target Detection processor with a significant computational cost reduction.

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

<span lang="EN-US">For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms. In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF). An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms.</span>

Chaotification of Sine-series maps based on the internal perturbation model

In this paper, a chaotification method based on the internal perturbation model (IPM) is proposed. The single-perturbation and the multiple-perturbations are introduced. The Sine map is taken as an example. Moreover, this method can be generalized to high-dimensional maps that contain sine, no matter where the sine term is in the system equation. we further apply IPM to an integer-order and a fractional-order Sine-series map. For those new maps, the parameter space and FuzzyEn complexity are significantly extended while maintaining the topological structure of system. These complex behaviors and digital signal processing (DSP) implementation validate the effectiveness of IPM and make it have the potential of better secure communication and encryption.

Non-Orthogonal Discrete Multi-Tone: Toward Higher Spectral Efficiency for Optical Networks

Achieving higher spectral efficiency is an efficient approach to address the bandwidth crisis of optical networks, but it faces significant technical challenges. High-spectral-efficiency non-orthogonal frequency-division multiplexing (NOFDM) has been proposed for meeting the requirement of optical networks' capacity upgrade. Compared to orthogonal frequency-division multiplexing, NOFDM can achieve higher spectral efficiency by compressing the subcarrier spacing narrower than the Nyquist orthogonal spacing, but this inevitably induces inter-carrier interference (ICI). ICI cancellation algorithms are crucial in NOFDM for correctly recovering the transmitted signal at the expense of extra processing power. Nowadays, processing power is no longer the obstacle to eliminate ICI due to the rapid development of application-specific integrated circuits for efficient implementation of digital signal processing. In this article, fast multiplexing and demultiplexing for NOFDM are implemented based on inverse fast Fourier transform and fast Fourier transform, respectively. Meanwhile, three representative ICI cancellation algorithms are discussed, and one of them is experimentally implemented. Furthermore, we propose non-orthogonal discrete multitone (NODMT) by integrating the advantages of NOFDM and DMT, which has the potential to achieve improved spectral efficiency for future optical networks.

New Dynamic Fuzzy High Gain Observer Combined with a Nonlinear Control Approach for Performance Enhancement in WECS Based on DFIG: Design and DSP Implementation

The main purpose of this article is to develop and to implement on a TMS320F28335 Digital Signal Processor (DSP) a new robust nonlinear observer combined with a backstepping approach for wind energy conversion systems using grid-connected Doubly Fed Induction Generator (DFIG). The principal objective of this work is to synthesize a robust non-linear observer associated with a non-linear control law to realize the wind system control, based on DFIG, with the use of sensor minima. The backstepping approach is being implemented in order to improve setpoint tracking, ensure stability, robustness to any variations in parameters and disturbance rejection. A robust nonlinear observer based on a high gain dynamic fuzzy observer (DFHGO) is designed to solve the major problem of some observers’ approach especially the destabilizing effect of the peak phenomenon. To validate the proposed observer, a co-simulation platform (MATLAB/Simulink and DSP) is elaborated. The simulation results of the synthesis observers as well as its DSP implementation in the loop show that this enhanced combination increases the above-mentioned performance.

A hyperchaotic cycloid map with attractor topology sensitive to system parameters.

We propose herein a novel discrete hyperchaotic map based on the mathematical model of a cycloid, which produces multistability and infinite equilibrium points. Numerical analysis is carried out by means of attractors, bifurcation diagrams, Lyapunov exponents, and spectral entropy complexity. Experimental results show that this cycloid map has rich dynamical characteristics including hyperchaos, various bifurcation types, and high complexity. Furthermore, the attractor topology of this map is extremely sensitive to the parameters of the map. The x--y plane of the attractor produces diverse shapes with the variation of parameters, and both the x--z and y--z planes produce a full map with good ergodicity. Moreover, the cycloid map has good resistance to parameter estimation, and digital signal processing implementation confirms its feasibility in digital circuits, indicating that the cycloid map may be used in potential applications.

Characteristic Analysis of Fractional-Order Memristor-Based Hypogenetic Jerk System and Its DSP Implementation

In this paper, a fractional-order memristive model with infinite coexisting attractors is investigated. The numerical solution of the system is derived based on the Adomian decomposition method (ADM), and its dynamic behaviors are analyzed by means of phase diagrams, bifurcation diagrams, Lyapunov exponent spectrum (LEs), dynamic map based on SE complexity and maximum Lyapunov exponent (MLE). Simulation results show that it has rich dynamic characteristics, including asymmetric coexisting attractors with different structures and offset boosting. Finally, the digital signal processor (DSP) implementation verifies the correctness of the solution algorithm and the physical feasibility of the system.

Advanced Convolutional Neural Networks for Nonlinearity Mitigation in Long-Haul WDM Transmission Systems

Practical implementation of digital signal processing for mitigation of transmission impairments in optical communication systems requires reduction of the complexity of the underlying algorithms. Here, we investigate the application of convolutional neural networks for compensating nonlinear signal distortions in a 3200 km fiber-optic 11x400-Gb/s WDM PDM-16QAM transmission link with a focus on the optimization of the corresponding algorithmic complexity. We propose a design that includes original initialisation of the weights of the layers by a filter predefined through the training a single-layer convolutional neural network. Furthermore, we use an enhanced activation function that takes into account nonlinear interactions between neighbouring symbols. To increase learning efficiency, we apply a layer-wise training scheme followed by joint optimization of all weights applying additional training to all of them together in the large multi-layer network. We examine application of the proposed convolutional neural network for the nonlinearity compensation using only one sample per symbol and evaluate complexity and performance of the proposed technique.

Initial Value Determination of Chua System with Hidden Attractors and Its DSP Implementation

In this paper, a method for determining the initial value of the hidden attractors in the Chua system is studied. The initial value of the hidden attractors can be calculated quickly and accurately by the proposed method, and the hidden attractors can be found by numerical simulation. Then, the initial values of the hidden attractors are set accurately by digital signal processor (DSP), so as to the circuit realization of the chaotic system with hidden attractors is performed. The results show that the numerical simulation results of Matlab are consistent with the experimental results of DSP.

Single Sideband Transmission Employing a 1-to-4 ADC Frontend and Parallel Digitization

Distributed data-centers have emerged as a key architecture for future optical networks. This architecture relies on power and cost-efficient high-speed fiber optical connections over distances up to 80 km which can be densely wavelength-division multiplexed (WDM) in the C-band. Recently, single-polarization single sideband (SSB) direct detection (DD) has been considered as an attractive transmission scheme for achieving data rates beyond 100 Gb/s per channel over 80 km. The advantages of SSB DD transmission includes the simple transceiver architecture and the capability of electronic dispersion compensation. However, the required digitizer's bandwidth in a single-polarization SSB transmission is around four times higher than in those of a conventional dual-polarization coherent detection system offering the same data rate. This critical issue prevents the practical implementation of high-speed SSB digital signal processing (DSP) in CMOS ASIC. To address this problem, we consider in this work a 112 GSa/s SiGe HBT BiCMOS ADC frontend. Using this ADC front-end, we experimentally demonstrate a WDM SSB DD transmission at a net data rate of 200 Gb/s per channel over 80 km while using only 14 GHz of digitizer's bandwidth which is comparable to those of a full-coherent counterpart.