Implementation Of Digital Filters Research Articles

희소한 부호 자리수 계수를 갖는 FIR 필터 설계

광대역 통신 모뎀이나 초고해상도 비디오 코덱 등과 같이 높은 데이터율을 갖는 시스템을 하드웨어로 구현할 때에는 디지털 필터의 고속 구현이 필수적이다. 디지털 필터의 임계경로는 대부분 MAC (multiplication and accumulation) 연산 회로이므로 필터 계수의 0이 아닌 비트의 갯수가 희소하다면 하드웨어 비용이 적은 덧셈기로도 디지털 필터를 고속으로 구현할 수 있다. 압축센싱은 신호의 희소 표현이나 희소 신호의 복원에 우수한 성능을 보임이 최근 연구에서 보고되고 있다. 본 논문에서는 압축센싱에 기반한 디지털 FIR 필터의 CSD (canonic signed digit) 계수를 찾는 방법을 제안한다. 주어진 주파수 응답과의 오차를 최소하면서 탐욕적 방법으로 희소한 0이 아닌 부호자리수를 찾고 잘못 선택되었던 부호자리수는 제거하는 과정을 반복한다. 설계 예를 통해 제안된 방법으로 희소한 0이 아닌 CSD 계수의 FIR 필터를 설계할 수 있음을 보인다. High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters

In all the DSP(Digital Signal Processing) blocks such as digital filters, the filter coefficients are known before hand. Hence, full flexibility of the multiplier is not necessary. Multiplierless Multiple Constant Multiplication(MCM) technique can be used along with retiming for better digital filter optimization.This method is more efficient when compared to shift and add multiplications as intermediate results in MCM technique can be shared which reduces the area of multiplierless implementation of digital filters. The multiplierless filter circuit is further retimed to reduce the overall clock period which increases the clock frequency. Critical path and shortest path computations consume most of the time in retiming computation. The retiming minimizes the overall clock period by reducing the filter critical path. In the general purpose processor where actual retiming vectors are computed for digital filters, the speed with which the retiming transformation is performed suffers as the entire transformation code will be written in the form of a soft core. Hence, FPGA based path solver architecture are proposed in this paper can reduces the burden on general purpose processors while retiming. This work contributes to reduced processing time for retiming using FPGA based path solvers. Due to complexity and transistor size reduction, designing of VLSI architectures for DSP blocks has become very challenging. Automated Tools are required most often to introduce the products to market in a timely manner and to make the VLSI designs more stable, reliable and tractable. A framework called DiFiDOT(Digital Filter Design Optimization Tool) is developed in this work for synthesizing the optimized filter architectures. Finally, an application for Electrocardiography(ECG) is designed using MCM based retimed digital filters to remove the power supply interference, baseline drift and the broadband noise from the ECG signal.

Complementary metal‐oxide semiconductor implementation of digital filters for signal processing applications

Realisations of filters in signal processing using interconnects as delay elements have been presented. Normally, these filters are implemented using switched capacitor technique. However, in digital realisations of these filters, flip flops are used for obtaining the delays. Here, the implementation of these filters using interconnects has been presented. Moreover, filter architectures which acts as basic building blocks for other complex filter structures have been explored and discussed. Spice simulations of these basic building blocks are carried out using BSIM 4.3 50 nm technology with a supply voltage of 1 V.

SPEECH SIGNAL ANALYSIS FOR LINEAR FILTER BANKS OF DIFFERENT ORDERS

In speech signal processing using of filter banks is very important. The critical requirement is the sum of all the frequency responses of the band-pass filters of the filter bank i.e. composite frequency response be flat with linear phase. This paper deals with design and implementation of linear-phase FIR digital filters based filter bank flat with flat composite frequency response. The design is based on special properties of FIR filters by which excellent frequency response can be achieved. Keyword: Speech signal, FIR Filter, Composite frequency response. -------------------------------------------------------------------***------------------------------------------------------------------

An improved criterion for peak-to-peak realization of direct-form interfered digital filters employing saturation nonlinearities

Purpose– The purpose of this paper is to present a criterion for global asymptotic stability of state-space direct-form digital filters employing saturation arithmetic.Design/methodology/approach– An elegant use of inducedl∞approach (also known as a peak-to-peak approach) is made to develop a criterion for the overflow stability of state-space direct-form digital filters.Findings– The criterion not only guarantees asymptotic stability but also reduces the effect of external interference. The presented method yields better interference attenuation level as compared to a recently reported method. Numerical examples are given to illustrate the effectiveness of the proposed method.Practical implications– Digital filters are important dynamical systems in signal processing which are used for the processing of discrete signals. During the implementation of higher-order digital filter in hardware or software, introduction of external interference is unavoidable. Therefore, stability analysis of digital filters in the presence of external interference is of much practical importance.Originality/value– The main result of the paper is reported for the first time and it is useful to establish the asymptotic stability of digital filters in the presence of external disturbances.

Design and implementation of a multiband digital filter using FPGA to extract the ECG signal in the presence of different interference signals

In this paper, we propose a practical way to synthesize and filter an ECG signal in the presence of four types of interference signals: (1) those arising from power networks with a fundamental frequency of 50Hz, (2) those arising from respiration, having a frequency range from 0.05 to 0.5Hz, (3) muscle signals with a frequency of 25Hz, and (4) white noise present within the ECG signal band. This was done by implementing a multiband digital filter (seven bands) of type FIR Multiband Least Squares using a digital programmable device (Cyclone II EP2C70F896C6 FPGA, Altera), which was placed on an education and development board (DE2-70, Terasic). This filter was designed using the VHDL language in the Quartus II 9.1 design environment. The proposed method depends on Direct Digital Frequency Synthesizers (DDFS) designed to synthesize the ECG signal and various interference signals. So that the synthetic ECG specifications would be closer to actual ECG signals after filtering, we designed in a single multiband digital filter instead of using three separate digital filters LPF, HPF, BSF. Thus all interference signals were removed with a single digital filter. The multiband digital filter results were studied using a digital oscilloscope to characterize input and output signals in the presence of differing sinusoidal interference signals and white noise.

English

Digital Signal processing ranks among the most demanding applications of digital design concepts. It is a mature technology domain wherein the demands for enhanced performance and resource utilization have risen exponentially over the years. Finite impulse response (FIR) filters are used in Digital Signal Processing applications.Accuracy in Filter Designing is based on the Multiplication and accumulation of filter coefficients. This paper describes an approach to the VLSI implementation of digital filter which is flexible and provides superior to traditional approaches,low power, and area efficient Discrete Wavelet Transform architecture.

Fractional Euler analog-to-digital transform

In this paper, the design of fractional Euler transform which is the regular Euler transform where the digital delay operator z−1 is replaced by the ideal digital fractional delay operator z−α is presented. This introduced transform will be used in analog-to-digital transform to improve the accuracy of a digital filter equivalent to a given analog filter. However, because of the fractional delay operator z−α the proposed fractional Euler transform cannot be exactly implemented; only a limited implementation by means of infinite impulse response (IIR) digital filter can be achieved using approximation techniques. First, the fractional order α of the digital fractional delay operator z−α, for 0<α<0.5, is selected such that the relative error between the analog differentiator s and its equivalent digital one obtained by the fractional Euler transform is minimum. Then, the ideal digital fractional delay operator z−α is approximated by a digital IIR filter based on approximation of analog fractional order system leading to an IIR digital filter implementation of the fractional Euler transform. Illustrative examples are given to show the effectiveness of the fractional Euler analog-to-digital transform design. Finally, the design of low order digital differentiator using the proposed fractional Euler transform has been compared to the most recent designed analog-to-digital transforms.

An input-balanced realization-based structure for efficient implementation of digital IIR filters

Based on an input-balanced state-space realization, this paper derives a novel structure for efficient implementation of digital IIR filters. Such a structure is very similar to a normalized lattice and, for an N th order IIR filter, it possesses 5 N -1 non-trivial multipliers: two multipliers less than in a normalized lattice. Expressions for transfer function sensitivity measures and roundoff noise gain for the proposed structure are derived. Interestingly, it is shown that, when the filter is all-pass, the proposed structure requires 4 N multiplications in order to compute one output sample. Moreover, the corresponding roundoff noise gain is 4 N , much smaller than that of ( N +1) 2 given by the classical minimum roundoff state-space realizations. Results of simulations performed show that the proposed structure outperforms many classical ones in terms of implementation efficiency and robustness against finite-word-length effects.

Implementation of Digital Filters for the Removal of Artifacts from Electrocardiogram

Implementation of Digital Filters for the Removal of Artifacts from Electrocardiogram

Combine particle swarm optimization algorithm and canonical sign digit to design finite impulse response filter

The main contribution of this paper is to design a digital finite impulse response filter using the particle swarm optimization (PSO) algorithm combined canonical signed digit (CSD) representation. The design has been done based on matching certain frequency response and the filter coefficients in CSD representation with limited bits and some of coefficients to be zero, simultaneously. Using CSD representation, multipliers can substitute adders, shifters and subtractors. In filter design, the results show that combining PSO and CSD representations simultaneously is better than combining PSO and CSD sequentially. In addition the results, if the common adders and subtractors were computed for all filter coefficients that specified in CSD representation, significantly reduce the complexity of the hardware implementation of digital FIR filter.

Design and Implementation of Digital Filters for Mobile Healthcare Applications

Digital filtering process is often necessary to suppress the noisy characteristics embedded in biomedical signals such as ECG (Electrocardiogram), EEG (Electroencephalogram), and EMG (Electromyogram). As the availability and usage levels of Information and Communication Technology (ICT) increases, the applications of ubiquitous healthcare are expected to be accelerated in the form of pervasive healthcare utilizing the mobile devices for the next decade. One of these aspects, ambulatory ECG signals can be transmitted to a mobile device to offer telecardiology healthcare delivery. However the signal is vulnerable to base-line drift and power-line source fluctuations. With this aim, the digital filtering algorithms are implemented with an android platform smartphone to eliminate the noisy components especially in the ECG signal transmitted wirelessly from the wearable patch-style heart activity monitoring system. Graphical User Interface (GUI) is designed and implemented in an Android OS smartphone with programming multi-thread- Java modules to realize FIR (Finite Impulse Response Filter) and IIR (Infinite Impulse Response Filter). With applying our implemented digital filters built in a mobile device, we can conclude the fact that the artifacts in the ambulatory ECG signal due to base-line wandering and power- line instability can be efficiently reduced. 

Design and Implementation of digital FIR band stop filter for removal artifact from noisy ECG signal

In Digital signal processing, FIR Band stop Filter used to remove an unknown noise component in ECG signal lying within a 60 Hz frequency range. This paper gives the design appropriate signal processing algorithms for the refinement of ECG signals so that their characteristics may be extracted: this involves the design of a digital filter for the elimination of the power line interference and determines the waveform characteristics (PR, QRS and ST intervals and PR and ST segments) of the available ECG recording. Comparison of these characteristics with those of normal ECG recordings provides a way of identifying problems with the human cardiovascular system.

A bit too precise? Verification of quantized digital filters

Fixed-point digital filters are simple yet ubiquitous components of a wide variety of digital processing and control systems. Common errors in fixed-point filters include arithmetic round-off (truncation) errors, overflows and the presence of limit cycles. These errors can potentially compromise the correctness of the system as a whole. Traditionally, digital filters have been verified using a combination of design techniques from control theory and extensive testing. In this paper, we examine the use of formal verification techniques as part of the design flow for fixed-point digital filters. We study two classes of verification techniques involving bit-precise analysis and real-valued error approximations, respectively. We empirically evaluate several variants of these two fundamental approaches for verifying fixed-point implementations of digital filters. We design our comparison to reveal the best possible approach towards verifying real-world designs of infinite impulse response (IIR) digital filters. Our study compares the strengths and weaknesses of different verification techniques for digital filters and suggests efficient approaches using modern satisfiability-modulo-theories solvers (SMT) and hardware model checkers. This manuscript extends our previous work evaluating bounded verification, where a limited number of iterations of the system are explored, with unbounded verification, where an unlimited number of iterations of the system are considered. Doing so allows us to evaluate techniques that can prove the correctness of fixed-point digital filter implementations.

Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses

In this brief, an efficient implementation of reconfigurable warped digital filter with variable low-pass, high-pass, bandpass, and bandstop responses is presented. The warped filters, obtained by replacing each unit delay of a digital filter with an all-pass filter, are widely used for various audio processing applications. However, warped filters require first-order all-pass transformation to obtain variable low-pass or high-pass responses, and second-order all-pass transformation to obtain variable bandpass or bandstop responses. To overcome this drawback, the proposed method combines the warped filters with the coefficient decimation technique. The proposed architecture provides variable low-pass or high-pass responses with fine control over cut-off frequency and variable bandwidth bandpass or bandstop responses at an arbitrary center frequency without updating the filter coefficients or filter structure. The design example shows that the proposed variable digital filter is simple to design and offers substantial savings in gate counts and power consumption over other approaches.

The fast recursive computation of Tchebichef moment and its inverse transform based on Z-transform

The outputs of cascaded digital filters operating as accumulators are combined with a simplified Tchebichef polynomials to form Tchebichef moments (TMs). In this paper, we derive a simplified recurrence relationship to compute Tchebichef polynomials based on Z-transform properties. This paves the way for the implementation of second order digital filter to accelerate the computation of the Tchebichef polynomials. Then, some aspects of digital filter design for image reconstruction from TMs are addressed. The new proposed digital filter structure for reconstruction is based on the 2D convolution between the digital filter outputs used in the computation of the TMs and the impulse response of the proposed digital filter. They operate as difference operators and accordingly act on the transformed image moment sets to reconstruct the original image. Experimental results show that both the proposed algorithms to compute TMs and inverse Tchebichef moments (ITMs) perform better than existing methods in term of computation speed.

A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm

In this paper, we present an efficient distributed-arithmetic (DA) formulation for the implementation of block least mean square (BLMS) algorithm. The proposed DA-based design uses a novel look-up table (LUT)-sharing technique for the computation of filter outputs and weight-increment terms of BLMS algorithm. Besides, it offers significant saving of adders which constitute a major component of DA-based structures. Also, we have suggested a novel LUT-based weight updating scheme for BLMS algorithm, where only one set of LUTs out of M sets need to be modified in every iteration, where N=ML, N, and L are, respectively, the filter length and input block-size. Based on the proposed DA formulation, we have derived a parallel architecture for the implementation of BLMS adaptive digital filter (ADF). Compared with the best of the existing DA-based LMS structures, proposed one involves nearly L/6 times adders and L times LUT words, and offers nearly L times throughput of the other. It requires nearly 25% more flip-flops and does not involve variable shifters like those of existing structures. It involves less LUT access per output (LAPO) than the existing structure for block-size higher than 4. For block-size 8 and filter length 64, the proposed structure involves 2.47 times more adders, 15% more flip-flops, 43% less LAPO than the best of existing structures, and offers 5.22 times higher throughput. The number of adders of the proposed structure does not increase proportionately with block size; and the number of flip-flops is independent of block-size. This is a major advantage of the proposed structure for reducing its area delay product (ADP); particularly, when a large order ADF is implemented for higher block-sizes. ASIC synthesis result shows that, the proposed structure for filter length 64, has almost 14% and 30% less ADP and 25% and 37% less EPO than the best of the existing structures for block size 4 and 8, respectively.

Holistic Biquadratic IIR Filter Design for Communication Systems Using Differential Evolution

Digital IIR filter implementations are important building blocks of most communication systems. The chosen number format (fixed-point, floating-point; precision) has a major impact on achievable performance and implementation cost. Typically, filter design for communication systems is based on filter specifications in the frequency domain. We consider IIR filter design as an integral part of communication system optimisation with implicit filter specification in thetime domain(via symbol/bit error rate). We present a holistic design flow with the system's bit error rate as the main objective. We consider a discrete search space spanned by the quantised filter coefficients.Differential Evolutionis used for efficient sampling of this huge finite design space. We present communication system performance (based on bit-true simulations) and both measured and estimated receiver IIR chip areas. The results show that very small number formats are acceptable for complex filters and that the choice between fixed-point and floating-point number formats is nontrivial if precision is a free parameter.

Digital filter implementation over FPGA platform with LINUX OS

The embedded processors on FPGA's are a good tool to specific propose works. In this work we present how the FPGA is used to apply a Sobel filter to a set of images, also the step needed to set-up the entire system is described. An embedded processor, with a Linux distribution implemented is used to run a special compilation of C filter program, the filter is compared with the results obtained with a PC running the same filter, in the embedded system all the process runs in the FPGA and the exit file can be accessed by ftp or http server embedded into the Linux system.

Multistage Implementation of Multirate CIC Filters

In this paper a multistage multirate CIC filter has been compared with a FIR Filter. FIR filters are widely used in implementation of Digital Filters, but with some disadvantages like higher number of computational coefficients requirement and less computational speed. In this work we have shown that CIC filters are better choice than the single stage CIC or FIR Filters for multirate filtering structures and further improvement can be made by cascading different stages of CIC Filters.