Implementation Of Cryptosystem Research Articles

A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio

Over many years, Field Programmable Gated Ar-rays (FPGA) have been used as a target device for various prototyping and cryptographic algorithm applications. Due to the parallel architecture of FPGAs, the flexibility of cryptographic algorithms can be exploited to achieve high throughputs at the expense of very low chip area. In this research, we propose a low cost FPGA based cryptosystem named as Secure Cipher for high throughput to area ratio. The proposed Secure Cipher is implemented using full loop unroll technique in order to exploit the parallelism of the proposed algorithm. The proposed cryp-tosystem implementation achieved a throughput of 4600Mbps for encryption. The logic resource utilization of this implementation is 802 logic elements(LE) which yields a throughput to area ratio of 5.735Mbps/LE.

Auto Mutating Cryptosystem- An approach towards better security

The concept of learning systems has been an intriguing one since first appearance of Artificial Intelligence (AI) in literature. With the progress in each decade of research, new systems have been developed to suit a host of requirements and environments. However the idea of AI with a cryptosystem is relatively novel and is less explored. This paper discusses the implementation and analysis of multiple cryptosystems with an AI engine to provide better security for information. Here the attempt is made to combine number of cryptosystems with an AI engine to understand a situation where a hacker is trying to cryptanalyse data and prevent it from happening.

FPGA Implementation of Crypto-System based Wireless communication system

FPGA Implementation of Crypto-System based Wireless communication system

Optical Implementation of Asymmetric Cryptosystem Combined with D-H Secret Key Sharing and Triple DES

In this paper, an optical implementation of a novel asymmetrical cryptosystem combined with D-H secret key sharing and triple DES is proposed. The proposed optical cryptosystem is realized by performing free-space interconnected optical logic operations such as AND, OR and XOR which are implemented in Mach-Zehnder type interferometer architecture. The advantage of the proposed optical architecture provides dual outputs simultaneously, and the encryption optical setup can be used as decryption optical setup only by changing the inputs of SLMs. The proposed cryptosystem can provide higher security strength than the conventional electronic algorithm, because the proposed method uses 2-D array data, which can increase the key length surprisingly and uses 3DES algorithm, which protects against “meet in the middle” attacks. Another advantage of the proposed asymmetrical cryptosystem is that it is free to change the user’s two private random numbers in generating the public keys at any time. Numerical simulation and performance analysis verify that the proposed asymmetric cryptosystem is effective and robust against attacks for the asymmetrical cipher system.

Quantum-assisted QD-CFS signatures

Conventional cryptosystems collapse in face of attacks mounted with quantum computers, and thus research on quantum cryptography mainly focuses on symmetric cryptography, with which it is impossible to create complete quantum digital signatures. To address these issues, assuming the availability of quantum computers capable of performing Grover search, we explore their constructive influence on post-quantum cryptography. In particular, we show how a reasonably small quantum computer can assist in generating secure Courtois–Finiasz–Sendrier (CFS) signatures based on Goppa codes. This could be a step towards a practical implementation of full-fledged cryptosystems in a truly post-quantum scenario.

Efficient FPGA Implementation of RSA Coprocessor Using Scalable Modules

RSA Cryptosystem is considered the first practicable secure algorithm that can be used to protect information during the communication. The significance of high security and efficient implementations of RSA have formed the base of many cryptographic engineering researches. In fact, the implementation of RSA Cryptosystem is heavily based on modular arithmetic and exponentiation involving large prime numbers. In this paper, we propose an efficient FPGA design and architecture for RSA cryptosystem using ALTERA FPGA Hardware Kit. The proposed design comprises six levels: random two prime numbers, parallel multiplication of the prime numbers and their decremented values, get encryption key, get decryption key, encryption and decryption levels. As the modular multiplication is considered as the heart of RSA computations, Interleaved Algorithm was particularly chosen as an efficient solution to speed up the modular multiplication. The experimental part of this work has been synthesized for both ALTERA Cyclone IV EP4CE115F29C7 and VERTIX VII VC707 FPGA kits and resulted in a maximum frequencies of 15.725MHz, 17.629MHz respectively. These findings make our design comparable and a good choice for efficient RSA Cryptoprocessor design. The results for the FPGA implementation for EC design using these curves is also proposed in this paper.

A New Way of Design and Implementation of Hybrid Encryption to Protect Confidential Information from Malicious Attack in Network

A New Way of Design and Implementation of Hybrid Encryption to Protect Confidential Information from Malicious Attack in Network

Code-based cryptography on reconfigurable hardware: tweaking Niederreiter encryption for performance

Today’s public-key schemes that are either based on the factorization or the discrete logarithm problem. Since both problems are closely related, a major breakthrough in cryptanalysis (e.g., with the advent of quantum computing will render nearly all currently employed security system useless. Code-based public-key schemes rely on the alternative security assumption that decoding generic linear binary codes is NP-complete. Two code-based schemes for public-key encryption are available due to McEliece and Niederreiter. Although most researchers analyzed and implemented McEliece’s cryptosystem, we show in this work that the scheme by Niederreiter has some important advantages, such as smaller keys, more practical plain and ciphertext sizes and less computation complexity. In particular, we propose an efficient FPGA implementation of Niederreiter’s scheme that can encrypt more than 1.5 million plaintexts per seconds on a Xilinx Virtex-6 FPGA—outperforming all known implementations of other popular public-key cryptosystems so far.

Biometric cryptosystem based on discretized fingerprint texture descriptors

This paper focuses on a biometric cryptosystem implementation and evaluation based on a number of fingerprint texture descriptors. The texture descriptors, namely, the Gabor filter-based FingerCode, a local binary pattern (LBP), and a local direction pattern (LDP), and their various combinations are considered. These fingerprint texture descriptors are binarized using a biometric discretization method and used in a fuzzy commitment scheme (FCS). We constructed the biometric cryptosystems, which achieve a good performance, by fusing discretized fingerprint texture descriptors and using effective error-correcting codes. We tested the proposed system on a FVC2000 DB2a fingerprint database, and the results demonstrate that the new system significantly improves the performance of the FCS for texture-based fingerprints.

IMPLEMENTATION OF RSA KEY GENERATION BASED ON RNS USING VERILOG

RSA key generation is of great concern for implementation of RSA cryptosystem on embedded system due to its long processing latency. In this paper, a novel architecture is presented to provide high processing speed to RSA key generation for embedded platform with limited processing capacity. In order to exploit more data level parallelism, Residue Number System (RNS) is introduced to accelerate RSA key pair generation, in which these independent elements can be processed simultaneously. A cipher processor based on Transport Triggered Architecture (TTA) is proposed to realize the parallelism at the architecture level. In the meantime, division is avoided in the proposed architecture, which reduces the expense of hardware implementation remarkably. The proposed design is implemented by Verilog HDL and verified in matlab. A rate of 3 pairs per second can be achieved for 1024-bit RSA key generation at the frequency of 100 MHz.

Utilizing hard cores of modern FPGA devices for high-performance cryptography

This article presents a unique design approach for the implementation of standardized symmetric and asymmetric cryptosystems on modern FPGA devices. In contrast to many other FPGA implementations that algorithmically optimize the cryptosystems for being optimally placed in the generic array logic, our primary implementation goal is to shift as many cryptographic operations as possible into specific hard cores that have become available on many reconfigurable devices. For example, some of these dedicated functions are designed to provide large blocks of memory or fast arithmetic functions for Digital Signal Processing applications that can also be adopted for efficient cryptographic implementations. Based on these dedicated functions, we present specific design approaches that enable a performance for the symmetric AES block cipher (FIPS 197) of up to 55 GBit/s and a throughput of more than 30.000 scalar multiplications per second for asymmetric Elliptic Curve Cryptography over NIST’s P-224 prime (FIPS 186-3).

Modified Doubling Attack by Exploiting Chosen Ciphertext of Small Order

Power analysis can be used to attack many implementations of cryptosystems, e.g., RSA and ECC, and the doubling attack is a collision based power analysis performed on two chosen ciphertexts. In this paper, we introduced a modified doubling attack to threaten RSA and ECC implementations by exploiting only one chosen ciphertext of small order. To attack the RSA implementations we selected an input of order two while to attack the ECC implementations we exploited one chosen invalid point of small order on a cryptographically weak curve rather than on the original curve. We showed that several existing power analysis countermeasures for RSA and ECC implementations are still vulnerable to the proposed attack. To prevent the proposed attack, we suggested countermeasures for RSA as well as for ECC.

Implementation and analysis of various symmetric cryptosystems

This paper implements some of the widely used symmetric encryption techniques i.e. data encryption standard (DES), triple data encryption standard (3DES), advanced encryption standard (AES), BLOWFISH and RC4 in MATLAB software. After the implementation, these techniques are compared on some points. These points are avalanche effect due to one bit variation in plaintext keeping the key constant, avalanche effect due to one bit variation in key keeping the plaintext constant, memory required for implementation and simulation time required for different message lengths.

HARDWARE IMPLEMENTATION OF EFFICIENT MODIFIED KARATSUBA MULTIPLIER USED IN ELLIPTIC CURVES

The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and implementation of a reconfigurable Galois field multiplier, which is implemented using field programmable gate arrays (FPGAs). The multiplier of Galois field based on Karatsuba's divide and conquer algorithm allows for reasonable speedup of the top-level public key algorithms. Binary Karatsuba multiplier is more efficient if it is truncated at n-bit multiplicand level and use an efficient classic multiplier algorithm. In these work three levels to truncate Binary Karatsuba algorithm (4 bits, 8 bits and 16 bits) are chosen showing that 8 bits is the best level for minimum number of slices and time delay to truncate Binary Karatsuba algorithm which is designed on an Xilinx VirtexE XCV2600 FPGA device. The VHDL hardware models are building using Xilinx ISE foundation software. This work is able to compute GF (2191) multiplication in 45.889 ns. experimental results of comparing block and stream ciphers when used to secure VoIP in terms of end-to-end delay and subjective quality of perceived voice.

Concurrent error detection and correction in a polynomial basis multiplier over GF(2m)

Finite-field arithmetic has been widely used to speed up the encryption and decryption processes in many cryptosystems, especially elliptic curve cryptosystems. Regular finite-field arithmetic structures are suitable for very large-scale integration implementation of cryptosystems, making them attractive for mobile commerce applications. Multiplication is the critical operation in finite-field arithmetic operations. Fault-based cryptanalysis is a new cryptanalysis method that deliberately injects faults into cryptographic devices, and requires only a small amount of side-channel information to break common ciphers. Thus, effective and simple methods for protecting the encryption/decryption circuitry from attackers are required to ensure that cryptographic devices can produce accurate signatures. This study presents a polynomial basis (PB) multiplier over GF(2m) with concurrent error detection (CED), and proposes a PB multiplier with concurrent error correction (CEC). A parallel structure of function cells is used in the proposed multiplier array to reduce the propagation delay. The proposed PB multiplier with internal parallel structure can reduce the time complexity by 28%, and reduce the space complexity by 90%, compared with existing PB multipliers. Compared with existing PB multipliers with CED, the proposed device with CED has a 20% greater space complexity but a 30% less time complexity. To the author's knowledge, there is no previous report of PB multipliers with CEC capability. The proposed PB multiplier with CEC capability has a space complexity of only about 10% more and requires five more clock cycles than the proposed device without CEC capability.

Analysis of the efficiency of the Chor–Rivest cryptosystem implementation in a safe-parameter range

The Chor–Rivest cryptosystem, based on a high-density knapsack problem on a finite field F q h , was broken by Vaudenay for q ≈ 200 , h ≈ 24 , and h admitting a factor s verifying a certain condition. A new set of parameters q and h, which prevent this cryptosystem against Vaudenay’s attack, is presented and the computational aspects of its implementation in the Magma computational algebra system are analyzed.

Micro-Architectural Cryptanalysis

Cryptanalysis is the study of the methods used to obtain the meaning of encrypted information in a cryptosystem (typically, by finding a secret key) in nontechnical terms, its also called "code breaking" or "cracking the code." Micro-architectural analysis of cryptosystem implementations is a promising and interesting new security research direction that will continue to grow.

Visualization of cryptographic protocols with GRACE

In this paper we present GRACE (graphical representation and animation for cryptography education), a Java-based educational tool that can be used to help in teaching and understanding of cryptographic protocols. The tool adopts an active learning model that engages the learner by asking him to describe, in an exemplification of a real-world scenario, cryptographic protocols using simple primitives whose effects are visualized by means of animated sequences. To this end, the GRACE interface offers the learner the choice of several cryptographic and non-cryptographic related operations with their respective visualizations. By executing a series of these operations in the proper order, a teacher is able to provide a visual introductory description of several protocols. Moreover, since some of the cryptographic operations are not just simulated but concretely implemented, it can be used by students to see which elaborations are performed by each operation of a cryptographic protocol, and their effects on the represented scenario. GRACE comes equipped with the implementation of several cryptographic primitives and cryptosystems. Additional primitives and cryptosystems can easily be plugged in the system. Visualizations prepared with GRACE can be edited, navigated and saved in a file for playback. We also present the results of an experimental lesson taught in the Security on Communication Networks undergraduate course at the University of Salerno during the fall 2004 semester using GRACE. A copy of GRACE and some demo lessons featuring the visualization of some cryptographic protocols are available at http://www.dia.unisa.it/research/grace .

High-speed hardware implementations of Elliptic Curve Cryptography: A survey

For the last decade, Elliptic Curve Cryptography (ECC) has gained increasing acceptance in the industry and the academic community and has been the subject of several standards. This interest is mainly due to the high level of security with relatively small keys provided by ECC. To sustain the high throughput required by applications like network servers, high-speed implementations of public-key cryptosystems are needed. For that purpose, hardware-based accelerators are often the only solution reaching an acceptable performance-cost ratio. The fundamental question that arises is how to choose the appropriate efficiency-flexibility tradeoff. In this survey, techniques for implementing Elliptic Curve Cryptography at a high-speed are explored. A classification of the work available in the open literature in function of the level of efficiency and flexibility is also proposed. In particular, the subjects of reconfigurable, dedicated, generator, versatile and general purpose scalar multipliers are addressed. Finally, some words about future work that should be tackled are provided.

Fault attack on the balanced shrinking generator

Fault analysis, belonging to indirect attack, is a cryptanalysis technique for the physical implementation of cryptosystem. In this paper, we propose a fault attack on the Balanced Shrinking Generator. The results show that the attacker can obtain the secret key by analyzing faulty output sequences which is produced by changing control clock of one of Linear Feedback Shift Registers (LFSR). Therefore, the balanced shrinking generator has a trouble in hardware implementation.