Abstract

Over many years, Field Programmable Gated Ar-rays (FPGA) have been used as a target device for various prototyping and cryptographic algorithm applications. Due to the parallel architecture of FPGAs, the flexibility of cryptographic algorithms can be exploited to achieve high throughputs at the expense of very low chip area. In this research, we propose a low cost FPGA based cryptosystem named as Secure Cipher for high throughput to area ratio. The proposed Secure Cipher is implemented using full loop unroll technique in order to exploit the parallelism of the proposed algorithm. The proposed cryp-tosystem implementation achieved a throughput of 4600Mbps for encryption. The logic resource utilization of this implementation is 802 logic elements(LE) which yields a throughput to area ratio of 5.735Mbps/LE.

Highlights

  • Data security has been a topic of major interest since decades

  • We propose a novel cryptosystem named Secure Cipher and its Field Programmable Gated Arrays (FPGA) implementation

  • Reconfigurable hardware devices such as FPGAs play a vital role in assessing the performance of cryptographic block ciphers on hardware platform

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Summary

A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio

Abstract—Over many years, Field Programmable Gated Arrays (FPGA) have been used as a target device for various prototyping and cryptographic algorithm applications. Due to the parallel architecture of FPGAs, the flexibility of cryptographic algorithms can be exploited to achieve high throughputs at the expense of very low chip area. We propose a low cost FPGA based cryptosystem named as Secure Cipher for high throughput to area ratio. The proposed Secure Cipher is implemented using full loop unroll technique in order to exploit the parallelism of the proposed algorithm. The proposed cryptosystem implementation achieved a throughput of 4600Mbps for encryption. The logic resource utilization of this implementation is 802 logic elements(LE) which yields a throughput to area ratio of 5.735Mbps/LE

INTRODUCTION
FPGA based Cryptosystem
Motivation and Organization of Paper
PROPOSED CRYPTOSYSTEM AND FPGA IMPLEMENTATION
Secure Cipher
FPGA implementation
Results
Findings
CONCLUSION
Full Text
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