Circuit Implementation Research Articles

Variational Quantum Circuit Decoupling.

Decoupling systems into independently evolving components has a long history of simplifying seemingly complex systems. They enable a better understanding of the underlying dynamics and causal structures while providing more efficient means to simulate such processes on a computer. Here we outline a variational decoupling algorithm for decoupling unitary quantum dynamics-allowing us to decompose a given n-qubit unitary gate into multiple independently evolving sub-components. We apply this approach to quantum circuit synthesis-the task of discovering quantum circuit implementations of target unitary dynamics. Our numerical studies illustrate significant benefits, showing that variational decoupling enables us to synthesize general two- and four-qubit gates to fidelity that conventional variational circuits cannot reach.

Depth-Optimized Quantum Circuit of Gauss–Jordan Elimination

Quantum computers have the capacity to solve certain complex problems more efficiently than classical computers. To fully leverage these quantum advantages, adapting classical arithmetic for quantum systems in a circuit level is essential. In this paper, we introduce a depth-optimized quantum circuit of Gauss–Jordan elimination for matrices in binary. This quantum circuit is a crucial module for accelerating Information Set Decoding (ISD) using Grover’s algorithm. ISD is a cryptographic technique used in analyzing code-based cryptographic algorithms. When combined with Grover’s search, it achieves a square root reduction in complexity. The proposed method emphasizes the potential for parallelization in the quantum circuit implementation of Gauss–Jordan elimination. We allocate additional ancilla qubits to enable parallel operations within the target matrix and further reuse these ancilla qubits to minimize overhead from our additional allocation. The proposed quantum circuit for Gauss–Jordan elimination achieves the lowest Toffoli depth compared to the-state-of-art previous works.

An efficient quantum circuit implementation of ZUC-128 cipher with low T-depth

An efficient quantum circuit implementation of ZUC-128 cipher with low T-depth

Quantum Tunneling: From Theory to Error‐Mitigated Quantum Simulation

AbstractEver since the discussions about a possible quantum computer arised, quantum simulations have been at the forefront of possible utilities, with the task of quantum simulations being one that promises quantum advantage. Recently, advancements have made it feasible to simulate complex molecules using Variational Quantum Eigensolvers or study the dynamics of many‐body spin Hamiltonians. These simulations have the potential to yield valuable outcomes through the application of error mitigation techniques. Simulating smaller models carries a great amount of importance as well and currently, in the Noisy Intermediate Scale Quantum era, is more feasible since it is less prone to errors. The objective of this work is to examine the theoretical background and the circuit implementation of a quantum tunneling simulation, with an emphasis on hardware considerations. This study presents the theoretical background required for such implementation and highlights the main stages of its development. By building on classic approaches of quantum tunneling simulations, this study aims at improving the result of such simulations by employing error mitigation techniques, Zero Noise Extrapolation, and Readout Error Mitigation and uses them in conjunction with multiprogramming of the quantum chip, a technique used for solving the hardware under‐utilization problem that arises in such contexts.

Parameter-induced logical stochastic resonance in substrate potential with deformable sine-Gordon shape

Logical stochastic resonance (LSR) systems are physical nonlinear systems capable of robust Boolean logic operations under the influence of noise. While LSR systems suitable for electronic circuit implementation have been extensively studied, research on condensed matter LSR systems remains limited to constrained bistability with saturation characteristic. Considering the presence of periodic nonlinearities in many physical systems, a deformable sine-Gordon-shaped Remoissenet–Peyrard potential (RPP)-based LSR system is proposed for the first time in this work. Testing under both noise-free and noisy conditions proves the existence of parameter-induced LSR phenomena in the proposed system. Moreover, we find that a relatively wide potential well shape contributes to enhanced noise robustness in the RPP-based LSR system. Additionally, traditional polynomial nonlinearity-based LSR systems are compared with the proposed system. Regardless of whether the noise is Gaussian white noise or composite noise containing spiking pulses, the RPP-based LSR system exhibits superior robustness. The results demonstrate the exceptional advantages of the RPP-based LSR system and encourage further design of condensed matter LSR systems based on deformable periodic nonlinearities.

Computing high-degree polynomial gradients in memory

Specialized function gradient computing hardware could greatly improve the performance of state-of-the-art optimization algorithms. Prior work on such hardware, performed in the context of Ising Machines and related concepts, is limited to quadratic polynomials and not scalable to commonly used higher-order functions. Here, we propose an approach for massively parallel gradient calculations of high-degree polynomials, which is conducive to efficient mixed-signal in-memory computing circuit implementations and whose area scales proportionally with the product of the number of variables and terms in the function and, most importantly, independent of its degree. Two flavors of such an approach are proposed. The first is limited to binary-variable polynomials typical in combinatorial optimization problems, while the second type is broader at the cost of a more complex periphery. To validate the former approach, we experimentally demonstrated solving a small-scale third-order Boolean satisfiability problem based on integrated metal-oxide memristor crossbar circuits, with competitive heuristics algorithm. Simulation results for larger-scale, more practical problems show orders of magnitude improvements in area, speed and energy efficiency compared to the state-of-the-art. We discuss how our work could enable even higher-performance systems after co-designing algorithms to exploit massively parallel gradient computation.

Evaluating the Contribution of Model Complexity in Predicting Robustness in Synthetic Genetic Circuits.

The design-build-test-learn workflow is pivotal in synthetic biology as it seeks to broaden access to diverse levels of expertise and enhance circuit complexity through recent advancements in automation. The design of complex circuits depends on developing precise models and parameter values for predicting the circuit performance and noise resilience. However, obtaining characterized parameters under diverse experimental conditions is a significant challenge, often requiring substantial time, funding, and expertise. This work compares five computational models of three different genetic circuit implementations of the same logic function to evaluate their relative predictive capabilities. The primary focus is on determining whether simpler models can yield conclusions similar to those of more complex ones and whether certain models offer greater analytical benefits. These models explore the influence of noise, parametrization, and model complexity on predictions of synthetic circuit performance through simulation. The findings suggest that when developing a new circuit without characterized parts or an existing design, any model can effectively predict the optimal implementation by facilitating qualitative comparison of designs' failure probabilities (e.g., higher or lower). However, when characterized parts are available and accurate quantitative differences in failure probabilities are desired, employing a more precise model with characterized parts becomes necessary, albeit requiring additional effort.

Aluminum panel vibration reduction using single lead zirconate titanate and resonant circuit

This study aimed to reduce the vibration of an aluminum plate using a single lead zirconate titanate (PZT) electrical circuit. First, the natural frequencies and modes of the aluminum plate were analyzed using an analytical method to determine the dynamic characteristics of the plate. The frequency domain was used to derive the vibration characteristics of the acoustically excited aluminum plate. It was noted that the resonance region where the vibration of the panel increased rapidly was at 390 Hz, which was then set as the reduction target. Thereafter, the vibration reduction performances of the circuit that connects only the resistance element to the PZT panel and the resonant circuit that uses an inductor were compared. Through actual acoustic excitation, the vibration reduction of the aluminum panel using the PZT panel based on resistance and resonance circuits was validated. The results demonstrated that the vibration in the resonant frequency region of 384 Hz was reduced by 20% through the implementation of a resonant circuit, comprising an inductor and a resistor, added to a single PZT, whose weight was 0.08% of the weight of the aluminum panel. Therefore, this study confirmed that the vibration of aluminum plates can be effectively reduced using a low-weight PZT patch.

Ultrasound 3D beam-forming with distributed electrodes and frequency sub-band compounding

Abstract Array probes are commonly used in ultrasound equipment. These are transducers arranged in an array. This system requires multiple transmitter and receiver circuits, making it an expensive system; three-dimensional ultrasound imaging requires a two-dimensional array, which is even more expensive and difficult to popularize. We propose an imaging system with a single transducer and a single transmitter/receiver circuit for low-cost implementation of ultrasound imaging. The system uses a distributed electrode, which consists of multiple electrodes on a single transducer. Each electrode is connected to a single transmit/receive circuit. In this paper, we evaluate the performance of the proposed and existing array probe systems and systems by simulation.

Memristors-coupled neuron models with multiple firing patterns and homogeneous and heterogeneous multistability

Abstract Memristors are extensively used to estimate the external electromagnetic stimulation and synapses for neurons. In this paper, two distinct scenarios, i.e., an ideal memristor serves as external electromagnetic stimulation and a locally active memristor serves as a synapse, are formulated to investigate the impact of a memristor on a two-dimensional Hindmarsh–Rose neuron model. Numerical simulations show that the neuronal models in different scenarios have multiple burst firing patterns. The introduction of the memristor makes the neuronal model exhibit complex dynamical behaviors. Finally, the simulation circuit and DSP hardware implementation results validate the physical mechanism, as well as the reliability of the biological neuron model.

Memristive Circuit Implementation of Caenorhabditis Elegans Mechanism for Neuromorphic Computing.

To overcome the energy efficiency bottleneck of the von Neumann architecture and scaling limit of silicon transistors, an emerging but promising solution is neuromorphic computing, a new computing paradigm inspired by how biological neural networks handle the massive amount of information in a parallel and efficient way. Recently, there is a surge of interest in the nematode worm Caenorhabditis elegans (C. elegans), an ideal model organism to probe the mechanisms of biological neural networks. In this article, we propose a neuron model for C. elegans with leaky integrate-and-fire (LIF) dynamics and adjustable integration time. We utilize these neurons to build the C. elegans neural network according to their neural physiology, which comprises: 1) sensory modules; 2) interneuron modules; and 3) motoneuron modules. Leveraging these block designs, we develop a serpentine robot system, which mimics the locomotion behavior of C. elegans upon external stimulus. Moreover, experimental results of C. elegans neurons presented in this article reveals the robustness (1% error w.r.t. 10% random noise) and flexibility of our design in term of parameter setting. The work paves the way for future intelligent systems by mimicking the C. elegans neural system.

Test generation algorithm for QCA circuits targeting novel defects and its corresponding fault models

Considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology, Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives. QCA being at the molecular scale, defects are more likely to occur in it. Therefore, substantial development of QCA-oriented defects, its corresponding fault models and test generation is required. In this paper, a test generation algorithm for a QCA combinational circuit is proposed. The FAN (A Fanout Oriented) test generation algorithm is extended for QCA. The proposed Automatic Test Pattern Generator (ATPG) for QCA targets Single Stuck at Fault (SSF) set produced by novel Multiple Missing Cells (MMC) defects. The proposed ATPG is based on the QCA-oriented test generation properties and guided by proposed testability measures.The MCNC benchmark circuits are synthesized into QCA using proposed synthesis algorithms to check the effectiveness of the proposed ATPG. The ATPG is developed using C++ and tested on MCNC benchmark circuits. Further, ATPG-generated test vectors are validated at the QCA device level to demonstrate their correctness. The QCADesigner-E tool is used for the device-level implementation of the MCNC benchmark circuit.

Demonstration of 800°C SiC MOSFETs for Extreme Temperature Applications

Silicon Carbide (SiC) enhancement mode MOS electronics offer several benefits for realizing analog, digital and mixed signal electronics, but limitations on gate dielectric reliability has limited the adoption of MOS in high temperature application. In this work, we report GE’s lateral SiC MOSFETs exceeding previously reported temperature capabilities for SiC MOSFETs with experimental results that have shown that >500°C operation of SiC MOSFETS is possible with >400 hours demonstrated at 620°C, and short-term functionality demonstrated to 800°C. The result shows that MOS-based SiC electronics can continue to be a viable choice for circuit implementations at extreme temperatures >600°C.

A class of memristive Hénon maps

Abstract Memristor, the electronic component, is introduced in the Hénon map and is studied extensively. Several chaotic maps are proposed by constructing the memristors through nonlinear functions such as absolute value functions, trigonometric functions, and activation functions. It is found that in a part of the proposed chaotic maps, the local offset boosting of the system variable can be guided by a single parameter. Not only that, the generation of homogeneous multistability can be controlled by the initial conditions of the systems. Moreover, the number of homogeneous attractors produced changes when the system parameters are varied. In addition, the control of chaos can be achieved by adjusting the excitation frequency of the memristor. The theoretical results and numerical laws presented in this paper are verified by circuit implementation based on the microcontroller unit.

Hardware circuit implementation of transmitter and receiver based on UART protocol

In today's information age, the amount of data as an important information carrier is growing at an explosive rate. The importance of its transmission rate, stability, accuracy and other properties is gradually becoming more and more important. UART as a communication protocol is widely used in embedded and IoT systems. It is simpler and more direct than SP2 and I2C, which can greatly simplify the complexity of digital circuits and become one of the key directions to improve the performance of data transmission. In this paper, a digital circuit based on the transmitter and receiver side of the UART protocol has been constructed using the hardware description language of Verilog HDL to implement the function of receiving and transmitting data based on a clock signal of 50 MHz and a baud rate of 115200 bps as well as the use of an RS232 asynchronous serial interface. The simulation was carried out using Quartus II.

Tunable active noise control circuit topology for multiple-feature applications

A tunable active-noise-control (ANC) circuit topology for headsets used in different applications is presented in this article. In the current consumer headset market, ANC is a mature technology that is commonly applied to wireless headsets connected to smartphones for listening to music and making phone calls. The development of ANC headsets has resulted in low-cost and simple devices due to the built-in ANC registers in the digital circuit. Digital circuit implementation is important to provide ultra-low latency processing for different algorithms compared with using digital signal processors (DSPs). However, a limitation associated with these built-in ANC filters is that the ANC digital circuit has been designed only for the wireless headset consumer market. Consequently, ANC headsets can only be used for designated features. ANC tuned for planes by eliminating low-frequency engine noise has been commonly used in the past twenty years. Pass-through (PT) amplification is also commonly tuned to allow users to hear external sounds and have conversations without having to remove their headset. In addition, ANC and PT amplification are also not allowed to operate simultaneously on the existing chipsets. In this paper, an ANC circuit topology with ultra-low latency processing is presented, where the ANC response of the headset can be tuned without any restriction imposed by the built-in ANC filters. The proposed ANC circuit topology consists of a commercial ANC chipset with an external audio codec to provide tunable characteristics. It is achieved by fixed maximum noise cancellation of ANC chipset being modified by summing with the signal from audio-codec path via an audio mixer. Acoustic performance for several headset applications implemented using the proposed circuit is validated. This simple circuit topology can be easily developed and adapted to the current headset consumer market for consumer-selective ANC in different environments.

Simulink Modeling and Analysis of a Three-Dimensional Discrete Memristor Map

The memristor, a novel device, has been widely utilized due to its small size, low power consumption, and memory characteristics. In this paper, we propose a new three-dimensional discrete memristor map based on coupling a one-dimensional chaotic map amplifier with a memristor. Firstly, we analyzed the memristor model to understand its characteristics. Then, a Simulink model for this three-dimensional discrete memristor map was developed. Lastly, the complex dynamical characteristics of the system were analyzed via equilibrium points, bifurcation diagrams, Lyapunov exponent spectra, complexity, and multistability. This study revealed the phenomena of coexisting attractors and hyperchaotic attractors. Simulink modeling confirmed that the discrete memristors effectively enhanced the chaos complexity in the three-dimensional discrete memristor map. This approach addresses the shortcomings of randomness, the lack of ergodicity, and the small key space in a one-dimensional chaotic map, thereby enriching the theoretical analysis and circuit implementation of chaos.

Manufacturable Ti/ZrO2/Cu memristor-based synapses and biomimetic memory applications with circuit implementation

Manufacturable Ti/ZrO2/Cu memristor-based synapses and biomimetic memory applications with circuit implementation

Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model

Neuromorphic computing research is being actively pursued to address the challenges posed by the need for energy-efficient processing of big data. One of the promising approaches to tackle the challenges is the hardware implementation of spiking neural networks (SNNs) with bio-plausible learning rules. Numerous research works have been done to implement the SNN hardware with different synaptic plasticity rules to emulate human brain operations. While a standard spike-timing-dependent-plasticity (STDP) rule is emulated in many SNN hardware, the various STDP rules found in the biological brain have rarely been implemented in hardware. This study proposes a CMOS-memristor hybrid synapse circuit for the hardware implementation of a Ca ion-based plasticity model to emulate the various STDP curves. The memristor was adopted as a memory device in the CMOS synapse circuit because memristors have been identified as promising candidates for analog non-volatile memory devices in terms of energy efficiency and scalability. The circuit design was divided into four sub-blocks based on biological behavior, exploiting the non-volatile and analog state properties of memristors. The circuit was designed to vary weights using an H-bridge circuit structure and PWM modulation. The various STDP curves have been emulated in one CMOS-memristor hybrid circuit, and furthermore a simple neural network operation was demonstrated for associative learning such as Pavlovian conditioning. The proposed circuit is expected to facilitate large-scale operations for neuromorphic computing through its scale-up.

Series Editorial: Design and Implementation of Devices, Circuits, and Systems

Series Editorial: Design and Implementation of Devices, Circuits, and Systems