Analog Circuit Implementation Research Articles

Programmable CNN Analogue Chip for RD-PDE Multi-Method Simulations

Cellular Non Linear Networks can be useful applied for the solution of several types of Partial Differential Equations (PDEs). This paper will describe an analogue circuit implementation for the simulation of one-dimensional Reaction-Diffusion PDE with the possibility to set different boundary conditions as well as to select different discretization methodologies.

A bio-inspired companding strategy for spectral enhancement

This work presents a compressing-and-expanding, i.e., companding, strategy for spectral enhancement inspired by the operation of the auditory system. The companding strategy simulates the two-tone suppression phenomena of the auditory system and implements a soft local winner-take-all-like enhancement of the input spectrum. It performs multichannel syllabic compression without degrading spectral contrast. The companding strategy works in an analog fashion without explicit decision making, without the use of the fast Fourier transform, and without any cross-coupling between spectral channels. The strategy is useful in cochlear-implant processors, hearing aids, and speech recognition for enhancing spectral contrast. It is well suited to low-power analog circuit implementations.

Characteristics of poly‐Si TFTs required for System‐on‐Glass analog circuits

In this paper, we investigate on the characteristics of poly‐Si TFTs reuired for the implementation of analog circuits to be integrated with System‐on‐Glass (SoG). Matching requirements in terms of resistor values, threshold voltage and mobility of poly‐Si TFTs are derived as a function of the resolution of display system. Effective mobility of poly‐Si TFTs required for the realization of source driver is analyzed for various panel sizes.

Efficient training of neural gas vector quantizers with analog circuit implementation

This paper presents an algorithm for training vector quantizers with an improved version of the neural gas model, and its implementation in analog circuitry. Theoretical properties of the algorithm are proven that clarify the performance of the method in terms of quantization quality, and motivate design aspects of the hardware implementation. The architecture for vector quantization training includes two chips, one for Euclidean distance computation, the other for programmable sorting of codevectors. Experimental results obtained in a real application (image coding) support both the algorithm's effectiveness and the hardware performance, which can speed up the training process by up to two orders of magnitude.

Some stability criteria for cellular neural networks with sigmoidal nonlinearities

Some sufficient conditions are presented concerning the stability of equilibrium points of cellular neural networks (CNNs) with continuously differentiable sigmoidal nonlinearities. This type of nonlinearity represents a more realistic model of analogue circuit implementation than the usual piecewise-linear function.

A comparison of analog and digital circuit implementations of low power matched filters for use in portable wireless communication terminals

In this paper, analog and digital circuit realizations of a parallel programmable matched filter are examined. Through wide variations of the design space parameters, the general trend that is observed is that short, fast circuits tend to favor an analog implementation, while longer, slower circuits make a digital implementation more appropriate. A methodology is provided for choosing the preferable circuit-implementing technology when power consumption-as a function of data precision, filter length, operating frequency, technology scaling, and the maturity of the fabrication process-is used as the primary metric of comparison. It is shown that neither the analog nor the digital matched filter implementation is universally more power efficient than the other. Rather, a surface is mapped in the multidimensional design space where, on one side of this surface, a digital solution is preferable, while on the other side of the surface, an analog circuit is appropriate. Equations are given which delineate the position of this transitional surface in terms of the design space parameters, and example calculations and plots depicting the regions of dominance for the digital and analog matched filters for specific process and system parameters are presented.

A micropower analog circuit implementation of hidden Markov model state decoding

We describe the implementation of a hidden Markov model state decoding system, a component for a wordspotting speech recognition system. The key specification for this state decoder design is microwatt power dissipation: this requirement led to a continuous-time, analog circuit implementation. We describe the tradeoffs inherent in the choice of an analog design and explain the mapping of the discrete-time state decoding algorithm into the continuous domain. We characterize the operation of a ten-word (81-state) state decoder test chip.

High Performance ASIC Circuit for a Three-Phase Controlled Bridge Fed Static or Dynamic Load

SummaryThe increasing availability of single chip low cost Integrated Circuits has made it possible to reconsider conventional hardware designs for a variety of gating circuits. This paper presents a high performance Application Specific Integrated Circuit ASIC’s for a three-phase controlled bridge. The dynamic performance of the proposed ASIC is similar to an analog circuit implementation. The resolution of the firing angle is better than 0.043 degrees at 50 Hz. The good dynamic performance was verified by operating a six pulse bridge with the designed ASIC circuit and different firing angles. The bridge was supplying d-c voltage to R-L load or D-C motor. The test result (input a-c phase currents, d-c load current and d-c load voltage) confirm the excellent dynamic performance.

Analog circuit implementation and learning algorithm for nearest neighbor classifiers

Analog electronic circuits are implemented and learning algorithms are presented for Nearest Neighbor (NN) and f-NN. classifiers on the basis of the probabilistic formulation of these classifiers. Electronic networks are compact subthreshold MOS transistor circuits. In the learning algorithm, the place of prototypes and the variance of the probability distribution are optimized by using the steepest descent method for the Kullback-Leibler's information between the network output and the correct membership.

Diffusion network architectures for implementation of Gibbs samplers with applications to assignment problems

In this paper, analog circuit designs for implementations of Gibbs samplers are presented, which offer fully parallel computation. The Gibbs sampler for a discrete solution space (or Boltzmann machine) can be used to solve both deterministic and probabilistic assignment (association) problems. The primary drawback to the use of a Boltzmann machine for optimization is its computational complexity, since updating of the neurons is typically performed sequentially. We first consider the diffusion equation emulation of a Boltzmann machine introduced by Roysam and Miller (1991), which employs a parallel network of nonlinear amplifiers. It is shown that an analog circuit implementation of the diffusion equation requires a complex neural structure incorporating matched nonlinear feedback amplifiers and current multipliers. We introduce a simpler implementation of the Boltzmann machine, using a "constant gradient" diffusion equation, which eliminates the need for a matched feedback amplifier. The performance of the Roysam and Miller network and the new constant gradient (CG) network is compared using simulations for the multiple-neuron case, and integration of the Chapman-Kolmogorov equation for a single neuron. Based on the simulation results, heuristic criteria for establishing the diffusion equation boundaries, and neuron sigmoidal gain are obtained. The final CG analog circuit is suitable for VLSI implementation, and hence may offer rapid convergence.

Quantization effects in digitally behaving circuit implementations of Kohonen networks

Implementing a neural network on a digital or mixed analog and digital chip yields the quantization of the synaptic weights dynamics. This paper addresses this topic in the case of Kohonen's self-organizing maps. We first study qualitatively how the quantization affects the convergence and the properties, and deduce from this analysis the way to choose the parameters of the network (adaptation gain and neighborhood). We show that a spatially decreasing neighborhood function is far more preferable than the usually rectangular neighborhood function, because of the weight quantization. Based on these results, an analog nonlinear network, integrated in a standard CMOS technology, and implementing this spatially decreasing neighborhood function is then presented. It can be used in a mixed analog and digital circuit implementation.

Analogue circuit design and implementation of an adaptive resonance theory (ART) neural network architecture

Abstract An analogue circuit implementation is presented for an adaptive resonance theory neural network architecture, called the augmented ART-1 neural network (AART1-NN). The AART1-NN is a modification of the popular ARTl-NN, developed by Carpenter and Grossberg, and it exhibits the same behaviour as the ARTl-NN. The A ARTl-NN is a real-time model, and has the ability to classify an arbitrary set of binary input patterns into different clusters. The design of the AART1-NN circuit is based on a set of coupled nonlinear differential equations that constitute the AART1-NN model. The circuit is implemented by utilizing analogue electronic components such as operational amplifiers, transistors, capacitors, and resistors. The implemented circuit is verified using the PSpice circuit simulator, running on Sun workstations. Results obtained from the PSpice circuit simulation compare favourably with simulation results produced by solving the differential equations numerically. The prototype system developed here can be used as a building block for larger AARTI-NN architectures, as well as for other types of ART architectures that involve the AARTI-NN model.

High performance single-chip gating circuit for a phase-controlled bridge

The increasing availability of single-chip low cost microcontrollers has made it possible to reconsider conventional hardware designs for a variety of gating circuits. This paper, in particular, presents the design of a gating circuit for a six-pulse phase-controlled bridge utilizing a single-chip programmable microcontroller. The dynamic performance of the proposed gating circuit is similar to an analog circuit implementation. The resolution of the firing angle is better than 0.1 degrees at 60 Hz. Moreover, the system is designed to operate over a frequency range of 3 Hz to 120 Hz, and to automatically adapt to changes in line frequency. The experimental verification of the performance criteria are also presented. Finally, an example of a special application for a dual-bridge AC to DC converter is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analog circuit implementation of neural network with high precision weights

A current-mode MOS neuron circuit with 4-bit programmable weights is presented by using CMOS technology. The weights of the neuron have high resolution and also can easily be digitally stored. The resolution can be extended into high levels such as 8-bit, etc. by the design methodology presented in this paper. The operational principle of the neuron is discussed. Circuit simulation has been made by use of SPICE II. The results give a good agreement for the design requirements.

Circuit implementation of synchronized chaos with applications to communications.

An analog circuit implementation of the chaotic Lorenz system is described and used to demonstrate two possible approaches to private communications based on synchronized chaotic systems.

A review of median filter systems for analog signal processing

This paper presents a review of existing analog implementations of the median and other ranked-order filter operations. The basic properties of median signal processing are first reviewed. Different analog median filter architectural approaches and implementations, introduced by several authors, are then discussed. These include filters based on analog delay lines and either nonlinear selection networks or ramp voltage generators. The Linear-Median Hybrid filter concept is presented and two examples of analog circuit implementations are given. Finally, a neural network approach is discussed.

Existence of binary invariant sets in feedback neural networks with application to synthesis

The design of fully connected discrete-time neural networks, with threshold units, can be performed by solving a set of linear inequalities. Using this formulation, the design problem can be handled by several powerful algorithms. This approach is extended to the design of continuous-time neural networks with sigmoidal units, which represent a more realistic model of analog circuit implementations. The proposed method is based on some theoretical results proved in this paper.

Operational amplifiers for fast nuclear electronics applications

Two configurations of fast operational amplifiers are considered in this paper. They are intended as basic active elements for the implementation of analog circuits in nuclear electronics, for pulse widths shorter than 100 ns. Both operational amplifiers are theoretically analyzed and it is shown how they can be compensated for best operation in ifferent conditions for feedback network and external load. Practical circuits are also given with a discussion about their experimental performances that supply full validity to the theoretical analysis.