Advanced Encryption Standard Implementation Research Articles

Power Consumption Efficiency of Encryption Schemes for RFID

This paper provides a comparative analysis of AES (Advanced Encryption Standard) and Salsa20 algorithm implementations, focusing on power consumption efficiency in passive RFID (radio-frequency identification) tags and ultra-low-power devices. The main objective of this work is to determine which of these algorithms is more suitable to operate in these types of devices. For this purpose, ASIC (application-specific integrated circuit) implementations of AES and Salsa20 based on low-power approaches were developed and their power consumption was evaluated. The results demonstrate that Salsa20 power consumption is lower than AES (about 17%), indicating that Salsa20 is a much better choice than AES for passive RFID tags.

A Survey on the Advanced Encryption Standard (AES): A Pillar of Modern Cryptography

As the digital landscape expands and our reliance on secure data transmission grows, the adoption of encryption technologies has become paramount. Over time, we have witnessed a progression from rudimentary ciphering methods, like substitution ciphers, to the sophisticated algorithms of today, epitomized by the Advanced Encryption Standard (AES). AES’s ascendancy to the forefront of encryption can be attributed to its unparalleled security features, surpassing its predecessors such as the Data Encryption Standard (DES). AES boasts robust security measures, rendering it virtually impervious to conventional cryptographic attacks. Its resilience against decryption is underscored by its intricate encryption process, which involves intricate operations such as byte substitution, row shifting, column mixing and round key addition. Conversely, decryption reverses these steps, ensuring the confidentiality of encrypted data remains intact. Despite the emergence of various cryptographic attacks, none have posed a significant threat to a properly implemented Full-AES algorithm. Most attacks target incomplete implementations, highlighting the importance of proper implementation practices in maximizing AES’s security benefits. Beyond its security prowess, AES stands out for its efficiency, sustainability and simplicity. Despite its widespread adoption and robustness against cryptanalytic attacks, AES exhibits an intriguing phenomenon known as error propagation. Through theoretical analysis and empirical investigations, we elucidate the mechanisms by which errors propagate within AES, shedding light on the vulnerabilities they introduce. Additionally, we explore the implications of error propagation in practical scenarios, including its impact on cryptographic protocols, error correction mechanisms and overall system reliability. Our findings underscore the importance of comprehensively understanding and mitigating the effects of error propagation in AES implementations, offering insights into enhancing the resilience of cryptographic systems against unforeseen adversities.

Designing New AES and Implementing it with LFSR Key to Improve Data Security

Data security is an essential aspect of data communication and data storage. The security and confidentiality of the information has become a significant factor in the communication field. To provide high-level security against all kinds of unauthorized accesses, cryptographic algorithms have been applied to various fields such as medical and military applications. Several techniques for encryption and decryption are proposed to promote the security of the communication systems. Most powerful and significant part of the encryption is a key generation. Presently, hackers are able to break the key with help of the modern high computing machines. Advanced Encryption Standard (AES), a symmetric cryptographic algorithm, is acknowledged as the most secure algorithm for the cryptographic process globally. In this work, Novel design and implementation of AES with LFSR (Linear Feedback Shift Register) key for improving data security is presented. The novelty of this work is using LFSR with AES. The Performance of presented approach is evaluated in terms of speed, area and security. The performance of presented technique will provide effective and efficient security to data.

Efficient adaptive framework for securing the Internet of Things devices

The research on the Internet of Things (IoT) has made huge strides forward in the past couple of years. IoT has its applications in almost every walk of life, and it is being regarded as the next big thing that can change the way humans perceive about their daily life. Smart IoT devices of heterogeneous nature make an essential part of modern day IoT-based systems. The security of these devices is of paramount importance as they handle an enormous amount of critical data and its breach can lead to potentially life-threatening situations. To secure the IoT devices of heterogeneous nature, we formulated a weighted optimization problem in this work. The objective function of this problem is to secure the IoT devices while finding the best trade-off between their resource usage and throughput. To achieve the objective, we consider a pool of five different implementations of Advanced Encryption Standard (AES) cryptographic schemes that offer varied resources and throughput numbers. These implementation schemes are mapped to IoT devices of heterogeneous nature. The mapping is performed through a novel adaptive framework that can consider different weights for resources and throughput to eventually find the best trade-off between the resources and throughput of an IoT-based system. This framework considers the resource and throughput requirements of different IoT devices and uses the Hungarian algorithm to adaptively map different AES implementations on them. Extensive experimentation is performed where the best trade-off is found through varying resource and throughput weight combinations. The comparison of the proposed framework with random and greedy approaches is also performed. Comparison results show that the proposed framework adaptively secures the IoT-based system while providing better resource usage and throughput results. The proposed framework provides, on average, 11% and 17% better throughput and 3% and 13% better resource usage results as compared to random and greedy approach, respectively.

Probing attack of share‐serial threshold implementation of advanced encryption standard

The authors present the first security evaluation of the side-channel attack countermeasure called the share-serial threshold implementation proposed by Wegener and Moradi. In the share-serial threshold implementation, all the component functions are processed using a unified circuit thereby reducing total circuit area. They show that the share-serial threshold implementation is vulnerable to probing attack using a single probe. In the proposed attack, an attacker places a single probe on a wire in the unified circuit and read the target wire over multiple cycles. The attacker can recover unshared 1-bit intermediate value by combining the measured data. The attack highlights an interesting difference between side-channel analysis and probing attack. The authors also evaluate the number of cipher calls to attack the block cipher advanced encryption standard (AES).

New second‐order threshold implementation of AES

In this work, the authors propose some alternative hardware efficient masking schemes dedicated to protect the Advanced Encryption Standard (AES) against higher order differential power analysis (DPA). In general, the existing masking schemes all have in common an intrinsic trade-off between the two main parameters of interest, namely the generation of fresh random masking values and the cost of hardware implementation. The design of efficient masking schemes which are non-expensive in both aspects appears to be a difficult task. In this study, the authors propose a second-order threshold implementation of AES, which is characterised by a beneficial trade-off between the two parameters. More precisely, compared to the masking scheme of De Cnudde et al. at CHES 2016, which currently attains the best practical trade-off, the proposed masking scheme requires 28.4% less random masking bits, whereas the implementation cost is slightly increased for about 13.7% (thus the chip area is 1.4 kGE larger). This masking scheme has been used to implement AES on an field-programmable gate array (FPGA) platform and its resistance against the second-order DPA in a simulated attack environment has been confirmed.

AES Overhead Mitigation Using OpenMP

The Advanced Encryption Standard (AES) has been extensively used in many systems to provide security. However, many of the implementations are susceptible to Side Channel Attacks (SCA). To address the susceptibility, several researchers have proposed a number of countermeasures. Masking scheme is one of the countermeasures that are commonly used to counteract such attacks. In this paper, we investigate the overhead of the countermeasure in terms of execution time of the first order-masking scheme for the AES “Encryption part only”. To achieve that, we have implemented the sequential algorithm of the AES with single processor, and after that used OpenMP directives to reduce the overhead of the countermeasure. Subsequently, the result of the sequential algorithm has been compared with its parallel implementations using 2, 4, 6, and 8 processors. We show how parallel implementation of the AES offers better performance yet flexible enough for cryptographic algorithms. Compared to the sequential unmasked AES implementation, the best masking scheme for the first order using data parallelism shows a performance in terms of speed up around 5x when 8 threads are used.

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption

In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel four-terminal spin Hall effect-driven domain wall motion devices that could be employed as both nonvolatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy ~15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1 ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent nonvolatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ advanced encryption standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES energy-delay product can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively.

Implementation of Advanced Encryption Standard (AES) and QR Code Algorithm on Digital Legalization System

A certificate is an important document that its validity must be ascertained. Fraud over the originality of this document demands a high level of security to ensure that this document is genuine. The Digital Certificate Legalization system (DCL) can regulate and guarantee the mechanism of document validity procedure. By implementing AES and QR Code algorithm, the information contained in the photo-scan of the certificate can be authenticated. The results of the scan are encrypted by using the legalized code in AES Algorithm. The code will be translated using the QR Code and matched to the data contained in the server system. The system will confirm whether the certificate is original or not. In order to test the system, black box testing is applied for functionality check; capacity testing in terms of execution time and memory load of benchmark testing are also examined for system performance measurement. Finally, user response testing is conducted to identify the user acceptance towards the system. As the result, the implementation of AES and QR Code algorithm provides good performance, efficient, light, and fast execution responses (less than one second and less than one megabyte) in a legalized certification checking system.

Access-driven cache attack resistant and fast AES implementation

The traditional advanced encryption standard (AES) implementations based on four lookup tables (4-T) of 1 KB size, have high encryption performance, whereas face access-driven cache attack at the same time. In this paper, we present an AES implementation based on one lookup table of 512 B with optimised structure, named 1-T, to improve the access-driven cache attack resistant ability. Furthermore, we optimise the implementation of round function of 1-T to eliminate the speed influence from the shrunken lookup table. The experiment result shows that attack resistant ability of 1-T is much higher than 4-T's under the same cache setting; and encryption time of 1-T is increased by 43.5% and 106.3% than 4-T's on the ARM and the ×86 platform respectively, but storage overhead is only 28% of 4-T's.

Analysis on the AES Implementation with Various Granularities on Different GPU Architectures

The Advanced Encryption Standard (AES) is One of the most popular symmetric block cipher because it has better efficiency and security. The AES is computation intensive algorithm especially for massive transactions. The Graphics Processing Unit (GPU) is an amazing platform for accelerating AES. it has good parallel processing power. Traditional approaches for implementing AES using GPU use 16 byte per thread as a default granularity. In this paper, the AES-128 algorithm (ECB mode) is implemented on three different GPU architectures with different values of granularities (32,64 and 128 bytes/thread). Our results show that the throughput factor reaches 277 Gbps, 201 Gbps and 78 Gbps using the NVIDIA GTX 1080 (Pascal), the NVIDIA GTX TITAN X (Maxwell) and the GTX 780 (Kepler) GPU architectures.

Clock Glitch Fault Injection Attacks on an FPGA AES Implementation

The Advanced Encryption Standard (AES) algorithm has been widely used to secure communication systems. However, the encryption algorithm is vulnerable to fault injection attacks and various attack methods have been studied. Some methods are just proposed in theory and have not been validated in practice. In this paper, we actualize a fault injection attack on an FPGA AES implementation. We propose a method to generate the highly accurate clock glitch to inject faults in the encryption process. We show that if the frequency of the clock glitch is carefully selected, only 6 faulty ciphertexts are necessary to discover the secret key.

The Effect of Eight-Shuffling AES Implementations Techniques against Side Channel Analysis

Even though cryptographic algorithms embedded on physical devices guarantee theoretical security, they are vulnerable to side channel attacks that analyze correlations related to physical information such as power consumption and electromagnetic waves. Physical devices without any countermeasures are vulnerable to side channel analysis. The masking and shuffling techniques the most used countermeasures against side channel analysis. Masking techniques rely on the masking order, however, these techniques have a high computational cost. Shuffling techniques, on the other hand, are able to provide security without high computational cost. Recently, instead of using one countermeasure alone, a combination of them has been employed while still affording provable security at a relatively computational cost. Computational security is related to the complexity of shuffling when a shuffling technique has been employed. In this paper, we apply shuffling techniques of the Advanced Encryption Standard (AES) in a new way. Our technique involves to eight different implementations of AES. If our technique is proven safety, then we will combine masking techniques and our technique. So, we examine the theoretical versus experimentally analyzed number of power traces for the recovery key. Theoretically, our results show 64 times more shuffling complexity than a non-shuffling AES implementation. Experimentally, however, it has seven times greater shuffling complexity.

PERFORMANCE CHARACTERIZATION OF PIPELINED S-BOX IMPLEMENTATIONS FOR THE ADVANCED ENCRYPTION STANDARD

In this paper, we present a comprehensive investigation of the influence of pipeline configurations on the performance of ASIC implementations of the Advanced Encryption Standard (AES) substitution box (S-box) based on a composite field structure. We consider pipeline configurations for the S-box with a typical composite field structure by varying the number of pipeline stages and the placement approach of pipeline registers. Besides the conventional placement approach at the component level of the S-box, we adopt a new placement approach at the gate level to achieve a fine-grained pipeline. The performance of the pipelined S-boxes is characterized based on a 90-nm standard cell CMOS technology. The characterization shows that there is notable performance improvement in timing, area, power and/or energy efficiency by using an appropriate configuration compared with other configurations including non-pipelined implementations. These results are strong evidence that pipelined S-box implementations are not only suitable for high throughput AES implementations, but also valuable to resource-efficient AES implementations. In addition, it is also shown that pipelining provides many more performance options that allow more flexible implementation of the AES S-box compared with non-pipelined implementations.

Implementation of AES on FPGA

Advanced Encryption Standard (AES) a National Institute of Standards and Technology specification is an approved cryptographic algorithm that can be used for securing electronic data. Reprogrammable devices such as Field Programmable Gate Arrays (FPGA) are highly attractive option for hardware implementations of cryptographic algorithm AES as they offer a quicker and more customizable solution. This paper proposes an efficient FPGA implementation of advanced encryption standard (AES). We implement the AES encryption algorithm on Xilinx Spartan-3 FPGA and decryption is done on PC. The coding for encryption is done in VHDL language and for decryption in Visual Basic. To implement AES Rijndael algorithm on FPGA plain text of 128 bit data is considered. Advanced Encryption Standard (AES) RIJNDAEL on FPGA offers a better performance than any other cryptographic algorithms.

A fault-resistant implementation of AES using differential bytes between input and output

Pervasive computing environments focus on integrating computing and communications with the surrounding physical environment. As a potential threat in the physical environment, fault attacks using the injection of practical faults have been introduced for extracting secret keys stored in low-cost devices. In particular, the advanced encryption standard (AES) has been broken by various fault attacks, and satisfactory countermeasures have yet to be introduced. This paper proposes a new countermeasure that can prevent fault attacks by verifying differential bytes of input and output in the encryption process and the key expansion process, respectively. The results of computer simulations and fault injection experiments verify that the proposed countermeasure against fault attacks outperforms existing countermeasures in terms of fault detection and efficiency.

High Performance and Reliable Fault Detection Scheme for the Advanced Encryption Standard

Fault injection attacks are powerful cryptanalysis techniques against the Advanced Encryption Standard (AES) algorithm. These attacks are based on injecting faults into the structure of the AES to obtain confidential information. To protect the AES implementation against these attacks, a number of countermeasures have been proposed. In this paper, we proposed a fault detection scheme, based on the information redundancy, for the AES. We discuss the strengths and the weaknesses of this scheme against the fault attacks. Moreover, we conduct a comparative study between fault detection schemes from the literature in terms of fault detection capabilities and implementation cost. The simulation results show that the fault coverage achieves 99.998% for the proposed scheme. Moreover, the proposed detection scheme has been implemented on Xilinx Virtex-5 FPGA. Its fault coverage, area overhead, throughput and frequency degradation have been compared and it is shown that the proposed scheme allows a trade-off between the hardware overhead and the security of the AES.

Implementation of AES as a Custom Hardware using NIOS II Processor

In this paper Advanced Encryption Standard (AES) algorithm has been designed and implemented as custom hardware. The algorithm is controlled through C-code written in NIOS II IDE. AES as a custom hardware is interfaced with the system designed around NIOS II Processor using SOPC builder tool. AES is written in hardware in VHDL language and the interface is through GPIO (General Purpose Input / Output Port). AES implemented using data size of 128 bits, while the length of the key used is of 128 bits. The key size of AES used is of 128 bits, as it is secure from the different attacks in existence. The FPGA used is CYCLONE II from Altera. AES as a custom hardware increases the speed of encryption and serves as an accelerator and hence improves the performance of the system.

Low-Power Design of Hardware One-Time Password Generators for Card-Type OTPs

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

Comparative performance and energy consumption analysis of different AES implementations on a wireless sensor network node

Many of the diverse Wireless Sensor Network (WSN) applications, such as home automation, traffic control and medical patient monitoring, have a strong requirement for the confidentiality of sensing data. At the same time, the restricted resources of WSN nodes demand that applications are implemented as efficiently as possible. Recently, the Advanced Encryption Standard (AES) has been proposed as the preferable symmetric cipher for WSN applications. This paper presents a performance and energy consumption analysis of three AES implementations on a wireless sensor node. For each implementation the memory requirements, the execution time and the energy consumption are monitored. The results of the presented analysis show that while the hardware-supported AES is faster than the software implementations, it is less energy efficient due to increased power requirements of the additional hardware.