PERFORMANCE CHARACTERIZATION OF PIPELINED S-BOX IMPLEMENTATIONS FOR THE ADVANCED ENCRYPTION STANDARD

Abstract

In this paper, we present a comprehensive investigation of the influence of pipeline configurations on the performance of ASIC implementations of the Advanced Encryption Standard (AES) substitution box (S-box) based on a composite field structure. We consider pipeline configurations for the S-box with a typical composite field structure by varying the number of pipeline stages and the placement approach of pipeline registers. Besides the conventional placement approach at the component level of the S-box, we adopt a new placement approach at the gate level to achieve a fine-grained pipeline. The performance of the pipelined S-boxes is characterized based on a 90-nm standard cell CMOS technology. The characterization shows that there is notable performance improvement in timing, area, power and/or energy efficiency by using an appropriate configuration compared with other configurations including non-pipelined implementations. These results are strong evidence that pipelined S-box implementations are not only suitable for high throughput AES implementations, but also valuable to resource-efficient AES implementations. In addition, it is also shown that pipelining provides many more performance options that allow more flexible implementation of the AES S-box compared with non-pipelined implementations.