Implementation of AES S-Box Based on VHDL

Abstract

Rijndael is defined as the algorithm for the Advanced Encryption Standard (AES). This paper describes the design of AES and fast implementations of AES on hardware based on FPGA with VHDL. In this paper, the S-Box was synthesized using Xilinx ISE 8.1i VHDL Compiler and the construction procedure for implementing a 5 stage pipeline combinational logic based S-Box is presented and illustrated in a step-by-step manner.