Real-time Hardware Implementation Research Articles

Hardware Implementation for Triaxial Contact-Force Estimation from Stress Tactile Sensor Arrays: An Efficient Design Approach.

This paper presents a contribution to the state of the art in the design of tactile sensing algorithms that take advantage of the characteristics of generalized sparse matrix-vector multiplication to reduce the area, power consumption, and data storage required for real-time hardware implementation. This work also addresses the challenge of implementing the hardware to execute multiaxial contact-force estimation algorithms from a normal stress tactile sensor array on a field-programmable gate-array development platform, employing a high-level description approach. This paper describes the hardware implementation of the proposed sparse algorithm and that of an algorithm previously reported in the literature, comparing the results of both hardware implementations with the software results already validated. The calculation of force vectors on the proposed hardware required an average time of 58.68 ms, with an estimation error of 12.6% for normal forces and 7.7% for tangential forces on a 10 × 10 taxel tactile sensor array. Some advantages of the developed hardware are that it does not require additional memory elements, achieves a 4× reduction in processing elements compared to a non-sparse implementation, and meets the requirements of being generalizable, scalable, and efficient, allowing an expansion of the applications of normal stress sensors in low-power tactile systems.

A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination

A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination

Digital neutron-gamma discrimination algorithm using adaptive noise filter

Pulse shape discrimination of a liquid scintillator-based detector (BC501A) has been studied using a digital approach. The objective of this work is to develop a new neutron-gamma discrimination algorithm to improve the discrimination efficiency. The new approach is a combination of two parts. The first part uses an adaptive Sallen-Key filter to reduce noise in the pulse followed by traditional approaches of either charge comparison or time over threshold. The approach of adaptive Sallen-Key combined with time over threshold was found to have a much better capability to discriminate neutron events from that of gamma. The pulse shape discrimination performance obtained for a 5 inches by 5 inches (length by diameter) liquid scintillator detector using the combination of the adaptive Sallen-Key filter with time over threshold is found to be significantly higher compared to that obtained using traditional methods. Moreover, this combination has the potential for real-time hardware implementation.

Adaptive neuro fuzzy technology to enhance PID performances within VCA for grid-connected wind system under nonlinear behaviors: FPGA hardware implementation

Wind Energy Conversion Systems (WECSs) exhibit nonlinear behavior due to internal and external disturbances, which can significantly impact the control performance. Firstly, this paper proposes a Vector Control Approach (VCA) based on Adaptive Neuro Fuzzy (ANF) of Proportional Integral Derivative (PID) controllers for a variable speed Permanent Magnet Synchronous Generator (PMSG)-based WECS connected to the grid to address these issues. The proposed ANF-PID controller combines the robustness of the fuzzy logic with the neural network's performance to ensure high accuracy, excellent tracking, and robustness against the WECS's nonlinear behavior. The neural network automates the placement of fuzzy logic membership functions. Secondly, this paper suggests a real-time hardware implementation of the VCA based on ANF-PID using a Field Programmable Gate Array (FPGA) to reduce the processing time and the WECS's sampling period. The effectiveness of the VCA based on ANF-PID controllers is validated by conducting a numerical simulation within the Matlab-Simulink using the Xilinx System Generator tool, alongside an experimental in-the-loop hardware implementation using FPGA board. Different scenarios are conducted to validate the robustness and stability of the proposed VCA based on ANF-PID control schemes, which is compared to Conventional Fuzzy PID (C-FPID) and PID controllers. The results exhibit that the VCA based on ANF-PID controllers outperforms VCA-C-FPID and VCA-PID controllers in terms of precision, tracking accuracy, and robustness against the WECS's nonlinear behavior and the PMSG parameter variations. The performances of the proposed controllers are tested under some criteria. In fact, the proposed ANF-PID controller provides a Mean Absolute Error (MAE), a Mean Squared Error (MSE) and a Root Mean Squared Error (RMSE) of 8.1911 × 10−04, 8.4181 × 10−05 and 0.0092, respectively. Compared to the C-FPID controller, the proposed controller offers an improvement gain of 98.96 %, 99.61 %, and 93.79 % of MAE, MSE, and RMSE, respectively. When compared to the PID controller, its improvement is even more significant, with a reduction of 99.9919 %, 99.9999 %, and 99.9288 % of MAE, MSE, and RMSE, respectively. In addition, the ANF-PID-based VCA utilizes hardware resources on the FPGA efficiently, requiring only 65.60 % slices LUT, 0.28 % LUTRAM, and 22.99 % FF. This makes it a more cost-effective option compared to the VCA-C-FPID controller for diverse control systems.

Harmonizing power systems with a 13-level modified Packed U-Cells multi-level inverter: Design and implementation

Traditional multilevel inverter designs often face complexity challenges, prompting the need for a simplified solution. This study introduces and evaluates the performance of a Modified Packed U-Cells (MPUC) inverter in the realm of multilevel inverter technology. The study addresses challenges associated with conventional multilevel inverters and proposes the MPUC inverter as a solution to simplify the design complexity. The MPUC inverter, utilizing three DC sources and eight switches, presents a groundbreaking thirteen-level output waveform. The primary focus lies in assessing the inverter's performance in terms of Total Harmonic Distortion (THD) and output voltage. Utilizing MATLAB/Simulink, the inverter's performance is evaluated with and without Pulse Width Modulation (PWM) strategies. The results reveal a notable reduction in THD, from 26.25% to 9.91% post-filtering when PWM is not employed. Various multi-carrier Level-Shifted PWM strategies, including PDPWM, PODPWM, APODPWM, and COPWM, are explored to enhance output waveform smoothness and efficiency. Unequal Carrier strategies, specifically UEAPDPWM and UEAPODPWM, emerge as superior in THD management at different frequency ranges. The study further incorporates real-time hardware implementation of the proposed 13-level MPUC topology, highlighting the success of the UEAPD-PWM strategy in improving waveform quality. The research aims to establish a multilevel inverter design protocol meeting international standards and emphasizes the pivotal role of PWM techniques in enhancing waveform quality. This comprehensive evaluation contributes to advancing the field of multilevel inverter technology and sets a benchmark for future research in this domain.

MODELING OF A STANDALONE SOLAR PHOTOVOLATIC (PV) GENERATION SYSTEM

This brief discusses the Modelling of a Standalone solar Photovolatic (PV) generation system. In this work the simulation of the PV system in open loop mode is carried out in MATLAB/Simulink environment and the real time hardware implementation has also been done. The PV panel output is fed to an inverter which supplies power to domestic load such as fans, lights. A battery and charge controller are also used in the system. The two results have been compared. The simulation and hardware results have been found matching with each other. Key Words: PV system, OFF-grid, Batteries, Inverter and Load.

A novel argyle puzzle for partial shading effect mitigation with experimental validation

Reconfiguring partially shaded photovoltaic (PV) arrays emerges as a potent solution for mitigating power loss and prolonging the array’s lifespan. Among the proposed strategies, static reconfiguration involves a one-time rearrangement, necessitating a reliable and effective approach for universal application. However, existing literature often exhibits a significant deficiency in uniformly scattering shade across sub-arrays, leading to disparate row currents and multiple peaks in array characteristics. To address this challenge, this paper introduces an innovative approach known as the Argyle puzzle, designed to provide a one-time layout for a total-cross-tied (TCT) PV array. The Argyle puzzle comprises diamond-shaped patterns and eight intersecting diagonal areas, each uniquely numbered. This design aims to maximize the dispersion of shading patterns. The superiority of the Argyle puzzle is demonstrated across fifteen shading patterns, underscoring its advantages over recent literature. Furthermore, experimental validation through real-time hardware implementation confirms the practicality of this approach. Ultimately, employing the Argyle approach proves instrumental in mitigating power loss during partial shading, consolidating array characteristics into a singular peak, and significantly enhancing the overall harvested power of the PV array.

A Real-time P-SFA hardware implementation of Deep Neural Networks using FPGA

Machine Learning (ML) algorithms, specifically Artificial Neural Networks (ANNs), have proved their effectiveness in solving complex problems in many different applications and multiple fields. This paper focuses on optimizing the activation function (AF) block of the NN hardware architecture. The AF block used is based on a probability-based sigmoid function approximation block (P-SFA) combined with a novel real-time probability module (PRT) that calculates the probability of the input data. The proposed NN design aims to use the least amount of hardware resources and area while maintaining a high recognition accuracy. The proposed AF module in this work consists of two P-SFA blocks and the PRT component. The architecture proposed for implementing NNs is evaluated on Field Programmable Gate Arrays (FPGAs). The proposed design has achieved a recognition accuracy of 97.84 % on a 6-layer Deep Neural Network (DNN) for the MNIST dataset and a recognition accuracy of 88.58% on a 6-layer DNN for the FMNIST dataset. The proposed AF module has a total area of 1136 LUTs and 327 FFs, a logical critical path delay of 8.853 ns. The power consumption of the P-SFA block is 6 mW and the PRT block is 5 mW.

Divide-and-conquer-based RDO-free CU Partitioning for 8K Video Compression

8K (7689×4320) ultra-high definition (UHD) videos are growing popular with the improvement of human visual experience demand. Therefore, the compression of 8K UHD videos has become a top priority in the third-generation audio video coding standard (AVS3). However, as an important part of the coding standard promotion, the real-time hardware implementation for AVS3-based 8K UHD video intra coding is severely hindered, especially in the coding unit (CU) partition stage. To break through the limitation, this article proposes a divide-and-conquer-based rate-distortion-optimization-free (RDO-free) CU partitioning algorithm for efficient hardware implementation. Aimed at the complex CU partition in AVS3, we separately design a lightweight optimization for original partitioning rules to improve division efficiency and a decision tree-based RDO-free CU decision framework to eliminate the latency caused by the waiting for rate-distortion cost calculation in RDO strategy. Afterward, a divide-and-conquer-based hardware-friendly gradient difference calculating approach is devised to accelerate the learning feature extracting speed. To ensure that the proposed algorithm is sufficient to support the real-time CU partition for 8K videos, we also develop a hardware architecture based on FPGA. Experimental results illustrate that the software coding performance of our algorithm is significantly ahead of the efficient implementation uAVS3e for AVS3 and the reference software HM-16.20 for High Efficiency Video Coding (HEVC), even though there is 9.96% loss on BD-Rate Y. Considering its importance for the hardware implementation of AVS3-based 8K real-time encoder, the coding loss is acceptable. Moreover, the hardware simulation results on VU440 FPGA with Vivado 2019 show that our algorithm can support 61.12 frames per second (fps) CU partition for 8K UHD videos with only 0.00%, 0.00%, 1.01%, and 7.78% consumption of BRAM_18K, DSP48E, FF, and LUT, respectively. Additionally, with dual-path parallelism, 122.24 fps also can be implemented with controllable resource utilization, which achieves the state-of-the-art performance.

An ultra-fast and energy-efficient CNTFET-based image corner detection hardware for real-time image processing applications

In image processing and machine vision, corner detection is pivotal in diverse applications, including computer vision, 3D reconstruction, face detection, object tracking, and video technologies. Despite the wide usage, the real-time and energy-efficient hardware implementation of corner detection algorithms remains a critical challenge because of the computational resource limitations. On the other hand, owing to the complicated nature of corner detection algorithms, their hardware implementation has been limited to the graphics processing unit (GPU) and field programmable gate arrays (FPGA) platforms. In this regard, this work aims to propose a novel and ultra-efficient carbon nanotube field-effect transistor (CNTFET)-based hardware for image corner detection. Thanks to the proposed corner detection algorithm, the designed hardware has been realized using 2742 transistors with competitive accuracy. The proposed corner detection hardware indicated a remarkable salt-and-pepper noise immunity without using any noise reduction circuit. Our comprehensive simulations demonstrate 78%, 87%, and 94.5% total average improvements in delay, power, and energy compared to the other related corner detection hardware. Moreover, the proposed CNTFET-based corner detection hardware shows a 43 ps propagation delay, demonstrating its real-time operation. The proposed corner detection algorithm at the system level shows suitable accuracy metrics such as Recall, Precision, and error of detection (EoD) compared to the other well-known corner detectors. Our method has established a new pathway for real-time circuit-level hardware design for image processing and machine vision applications.

A Two-Degree-of-Freedom PID Integral Super-Twisting Controller Based on Atom Search Optimizer Applied to DC-DC Interleaved Converters for Fuel Cell Applications

This paper focuses on the real-time implementation of an optimal high-performance control applied to an interleaved nonisolated DC/DC converter designed for fuel cell applications. Three-phase interleaved boost converters are utilized to minimize input current undulation, increase efficiency, and provide a high output voltage in order to ensure the performance of the FC stack. The proposed control strategy contains an outer loop that generates the reference current based on a two-degree-of-freedom PID controller. This controller provides a robust setpoint tracking and disturbance rejection, which improves the system’s response and efficiency. A fast inner regulation loop based on a super-twisting integral sliding mode (STISM) algorithm is developed to achieve a fixed converter output voltage, equitable phase current sharing, and fast regulation against load disturbances in failure operation. The STISM algorithm exhibits a rapid convergence property of the sliding mode and effectively avoids the chattering phenomena frequently observed in conventional sliding modes. The proposed controller’s gains are determined using the atom search optimization algorithm, which ensures exceptional reliability and a high degree of robustness and stability of the controllers under a variety of operational conditions. This method is inspired from the behavior of atoms and their electrons during the excitation process leading to a one-of-a-kind optimization technique which contributes to the controller’s reliability. Using Matlab-Simulink simulation tools, the efficacy and performance of the designed control have first been evaluated and assessed and compared with other optimization algorithms, and then with a dual loop based on a PID controller. Then, they have been verified by real-time hardware implementation on a 1.2 KW prototype FC converter driven by the dSPACE-1104 card under a variety of tests. The suggested approach offers impressive experimental results in dynamic and steady states.

Real-time energy-efficient software and hardware implementations of a QCSP communication system

In the Internet of Things, the energy efficiency of communications is crucial. Thus, using data-less preambles to detect frames is suboptimal. A preamble-less physical layer named “Quasi-Cyclic Short Packet (QCSP)” proposed a solution. However, the high computational complexity of the receiver makes the implementation challenging. This paper studies the feasibility and efficiency of real-time software and hardware QCSP systems. Several highly efficient transmitter implementations are presented, demonstrating the relevance of the approach. The parallelization and optimization strategies are elaborated for both software and hardware receiver implementations. They allowed software implementations with throughputs above 50 kb/s (maximum for the LoRa standard), consuming as low as 27 μJ/b. Thanks to detailed algorithm refinements, the throughtput even exceeded 250 kb/s on FPGA using High-Level Synthesis methodology, for an estimated consumption of 3.9 μJ/b. The results support the viability of the QCSP approach for cloud-RAN and edge computing in Low-Power Wide-Area Networks.

Real time implementation of a new seven level multilevel inverter with design considerations for feasible and reliable operation

SummaryFuture power electronics is moving towards compact, economical, feasible, and reliable inverters for integration with renewable energy sources and energy efficient drive schemes. Multilevel inverters (MLIs) are becoming more prominent candidates for such medium and high power applications. Though their attractive performance offers a better choice, the real time implementation of MLIs suffer with higher part count, compatibility of bidirectional switches, complementary conditions, number of transitions, polarity conversion module, and reliability. In order to bridge this gap, this work has come up with a new seven level symmetric MLI for utility applications. The abovementioned design parameters have been considered in the proposed MLI that promotes feasible and reliable operation for real time implementation. To defend this proposed topology, recent symmetric seven level MLI topologies have been compared and the results are compiled from constructional, operational, and performance aspects using Matlab/SIMULINK. The performance indices quantified for the analysis include part count, total harmonic distortion (THD), complementary conditions, number of transitions, polarity conversion module, switching losses, and reliability in terms of failure rate. The proposed topology has been validated through real time hardware implementation in which Atmega 2560 microprocessor is deployed for pulse generation.

Real-time fast learning hardware implementation

Machine learning algorithms are widely used in many intelligent applications and cloud services. Currently, the hottest topic in this field is Deep Learning represented often by neural network structures. Deep learning is fully known as deep neural network, and artificial neural network is a typical machine learning method and an important way of deep learning. With the massive growth of data, deep learning research has made significant achievements and is widely used in natural language processing (NLP), image recognition, and autonomous driving. However, there are still many breakthroughs needed in the training time and energy consumption of deep learning. Based on our previous research on fast learning architecture for neural network, in this paper, a solution to minimize the learning time of a fully connected neural network is analysed theoretically. Therefore, we propose a new parallel algorithm structure and a training method with over-tuned parameters. This strategy finally leads to an adaptation delay and the impact of this delay on the learning performance is analyzed using a simple benchmark case study. It is shown that a reduction of the adaptation step size could be proposed to compensate errors due to the delayed adaptation, then the gain in processing time for the learning phase is analysed as a function of the network parameters chosen in this study. Finally, to realize the real-time learning, this solution is implemented with a FPGA due to the parallelism architecture and flexibility, this integration shows a good performance and low power consumption.

Real time hardware implementation of discrete sliding mode fuzzy controlled buck converter using digital signal processor

This paper deals with the real time hardware implementation of discrete sliding mode fuzzy control (DSMFC) for buck converter using digital signal processor (DSP). Applications like electric vehicle suspension control, flight dynamic control, robot position control and engine throttle position control; sliding mode control (SMC) plays a major role. Hardware realization is difficult with SMC strategy due to the continuous gain change results in chattering problem and actuator or contact may break. To resolve this problem the fuzzy logic (FL) approach has combined with the robust technique discrete sliding mode control (DSMC) to develop a new strategy for DSMFC. The mathematical modeling of the controller is done using MATLAB/Simulink software and practical design of the converter is also realized. The robustness of the controller is proved by introducing sudden change in input voltage as well as load with the help of switching circuit in hardware realization. The obtained practical results are verified by comparing with the simulation output and reference value.

A Deep Learning Framework for Automatic Sleep Apnea Classification Based on Empirical Mode Decomposition Derived from Single-Lead Electrocardiogram.

Background: Although polysomnography (PSG) is a gold standard tool for diagnosing sleep apnea (SA), it can reduce the patient’s sleep quality by the placement of several disturbing sensors and can only be interpreted by a highly trained sleep technician or scientist. In recent years, electrocardiogram (ECG)-derived respiration (EDR) and heart rate variability (HRV) have been used to automatically diagnose SA and reduce the drawbacks of PSG. Up to now, most of the proposed approaches focus on machine-learning (ML) algorithms and feature engineering, which require prior expert knowledge and experience. The present study proposes an SA detection algorithm to differentiate a normal and apnea event using a deep-learning (DL) framework based on 1D and 2D deep CNN with empirical mode decomposition (EMD) of a preprocessed ECG signal. The EMD is ideally suited to extract essential components which are characteristic of the underlying biological or physiological processes. In addition, the simple and compact architecture of 1D deep CNN, which only performs 1D convolutions, and pretrained 2D deep CNNs, are suitable for real-time and low-cost hardware implementation. Method: This study was validated using 7 h to nearly 10 h overnight ECG recordings from 33 subjects with an average apnea-hypopnea index (AHI) of 30.23/h originated from PhysioNet Apnea-ECG database (PAED). In preprocessing, the raw ECG signal was normalized and filtered using the FIR band pass filter. The preprocessed ECG signal was then decomposed using the empirical mode decomposition (EMD) technique to generate several features. Several important generated features were selected using neighborhood component analysis (NCA). Finally, deep learning algorithm based on 1D and 2D deep CNN were used to perform the classification of normal and apnea event. The synthetic minority oversampling technique (SMOTE) was also applied to evaluate the influence of the imbalanced data problem. Results: The segment-level classification performance had 93.8% accuracy with 94.9% sensitivity and 92.7% specificity based on 5-fold cross-validation (5fold-CV), meanwhile, the subject-level classification performance had 83.5% accuracy with 75.9% sensitivity and 88.7% specificity based on leave-one-subject-out cross-validation (LOSO-CV). Conclusion: A novel and robust SA detection algorithm based on the ECG decomposed signal using EMD and deep CNN was successfully developed in this study.

High-impedance fault detection on downed conductor in overhead distribution networks

High impedance faults (HIF) may occur in the medium voltage distribution systems and constitute a danger to human beings. Many cases of HIF are caused due to downed power cables in the distribution network. These cables in contact with the ground generate a great risk to the population, animals and fire risk. In this paper, a methodology for detecting HIF, generated by cable breakage, is presented. The algorithm is based on the analysis of the harmonic and symmetrical components of the current. The method aims to gain reliability in HIF detection, where the detection of conductor breakage incorporated into the method allows a better distinction of HIF from other events. A distribution network based on a Brazilian real feeder was implemented, as well as two well know HIF models. The method is validated using real-time digital simulations and hardware implementation, or HIL (hardware-in-the-loop) concept with OPAL-RT real-time simulator. A comparison with other methods is also performed in order to evaluate the performance of the method. The results show that the proposed methodology has presented a better performance under different types of HIF, models of HIF, and achieved a general accuracy of 90% and security of 100% for the tests performed.

Cost-effective test-bed for secure visible-light communication

This study presents a real-time hardware implementation of a novel physical layer security algorithm developed for visible-light communications (VLCs) based on precoded spatial modulation (SM). The demonstration was carried out on a low-cost 70 cm × 40 cm × 40 cm miniature room model with four light-emitting diodes (LEDs) as a test-bed for conducting experiments in the field of VLC. The test-bed is a 10:1 shrunk replica of a conventional room and can be built with simple office supplies totaling <$10, excluding drive and collection optoelectronic components. While being cost-friendly, the test-bed also allows for (i) integrating optical components and (ii) carving desired window and door patterns with different cardboard color tones. Hence, the effects of reflections from different colored walls and the effect of external light sources can be observed on the performance of the secure VLC system. We successfully demonstrate the operation of the zero-forcing precoder and the SM on the built set up to provide robust and secure communication among the transmitting LEDs and the receivers, representing the legitimate user and the eavesdropper, for the first time in the literature. The secrecy capacity improvement is also noted, validating the proposed approach in realistic environments.

Adapting a Dehazing System to Haze Conditions by Piece-Wisely Linearizing a Depth Estimator.

Haze is the most frequently encountered weather condition on the road, and it accounts for a considerable number of car crashes occurring every year. Accordingly, image dehazing has garnered strong interest in recent decades. However, although various algorithms have been developed, a robust dehazing method that can operate reliably in different haze conditions is still in great demand. Therefore, this paper presents a method to adapt a dehazing system to various haze conditions. Under this approach, the proposed method discriminates haze conditions based on the haze density estimate. The discrimination result is then leveraged to form a piece-wise linear weight to modify the depth estimator. Consequently, the proposed method can effectively handle arbitrary input images regardless of their haze condition. This paper also presents a corresponding real-time hardware implementation to facilitate the integration into existing embedded systems. Finally, a comparative assessment against benchmark designs demonstrates the efficacy of the proposed dehazing method and its hardware counterpart.

Multiplier-Free Parallel Fixed-Point Adaptive Equalizer for Real-Time Digital Coherent Communication

Multiplier-free adaptive equalizers are significant for improving utilization, reducing costs, and ensuring robustness in real-time hardware implementation. In this letter, we demonstrate that using only one bit shift and one XOR operation to replace a real multiplier is a feasible and low-complexity way to obtain a multiplier-free parallel fixed-point adaptive equalizer (PFAEQ). The performances of the multiplier-free PFAEQ (MF-PFAEQ) are verified by a 112 Gbits/s polarization multiplexing quadrature phase shift keying (PM-QPSK) back-to-back experiment. It can be found that, under different parallels and different bit width of signals, MF-PFAEQ shows similar performances to traditional PFAEQ. Besides, in some cases, compared with the traditional PFAEQ, MF-PFAEQ also shows the similar convergent speed. In addition, according to the Quartus 15.0 synthesis, compared to traditional PFAEQ, the logic utilization and total registers of MF-PFAEQ reduce by 51.8% and 45.2%, respectively. This study is novel in using rather less shift operations to obtain a multiplier-free adaptive equalizer.