FPGA Implementation Research Articles

Advantages of unsupervised learning analysis methods in single-trace SCA attacks

Machine learning techniques are commonly employed in the context of Side Channel Analysis attacks. The clustering algorithms can be successfully used as classifiers in single execution attacks against implementations of Elliptic Curve point multiplication known as kP operation. They can distinguish between the processing of ‘ones’ and ‘zeros’ during secret scalar processing in the binary kP algorithm. The successful SCA performed by designers can aid in recognizing the leakage sources in cryptographic designs and lead to improvement of the cryptographic implementations. In this work we investigate the influence of the hamming weight of scalar k on the success rate of the single-trace attack. We used the clustering method K-means and the statistical method the comparison to the mean. We analysed simulated power traces and power traces of an FPGA implementation to conclude that K-means, unlike the comparison to the mean, was able to deal with extracting the scalar even when it is consisted of less than 30% of ‘ones’ and more than 70% of ‘ones’.

FPGA implementation of robust and low complexity template-based watermarking for digital images

FPGA implementation of robust and low complexity template-based watermarking for digital images

Scalable Data Concentrator with Baseline Interconnection Network for Triggerless Data Acquisition Systems

Triggerless data acquisition systems (DAQs) require that the data stream is transmitted from multiple links and into the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g., PCI Express) uses. In that process, the unneeded data must be eliminated, and a dense stream of useful DAQ data must be created. Additionally, the time order of the data should be preserved. This paper presents a new solution using the Baseline Network with Reversed Outputs (BNRO) for high-speed data routing. A thorough analysis of the network’s operation enabled increased scalability compared to the previously published concentrator based on an 8 × 8 network. The solution may be scaled by adding additional layers to the BNRO network while minimizing resource consumption. Simulations were performed for four and five layers (16 and 32 inputs). The FPGA implementation and tests in the actual hardware were successfully performed for 16 inputs. The pipeline registers may be added in each layer independently, shortening the critical path and increasing the maximum acceptable clock frequency.

Complex-Exponential-Based Bio-Inspired Neuron Model Implementation in FPGA Using Xilinx System Generator and Vivado Design Suite.

This research investigates the implementation of complex-exponential-based neurons in FPGA, which can pave the way for implementing bio-inspired spiking neural networks to compensate for the existing computational constraints in conventional artificial neural networks. The increasing use of extensive neural networks and the complexity of models in handling big data lead to higher power consumption and delays. Hence, finding solutions to reduce computational complexity is crucial for addressing power consumption challenges. The complex exponential form effectively encodes oscillating features like frequency, amplitude, and phase shift, streamlining the demanding calculations typical of conventional artificial neurons through levering the simple phase addition of complex exponential functions. The article implements such a two-neuron and a multi-neuron neural model using the Xilinx System Generator and Vivado Design Suite, employing 8-bit, 16-bit, and 32-bit fixed-point data format representations. The study evaluates the accuracy of the proposed neuron model across different FPGA implementations while also providing a detailed analysis of operating frequency, power consumption, and resource usage for the hardware implementations. BRAM-based Vivado designs outperformed Simulink regarding speed, power, and resource efficiency. Specifically, the Vivado BRAM-based approach supported up to 128 neurons, showcasing optimal LUT and FF resource utilization. Such outcomes accommodate choosing the optimal design procedure for implementing spiking neural networks on FPGAs.

FPGA Design and Implementation of Improved DFxLMS Algorithm for Compressor Noise Cancellation System

FPGA Design and Implementation of Improved DFxLMS Algorithm for Compressor Noise Cancellation System

A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application

A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application

ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks

‘‘Extreme edge” 1 devices, such as smart sensors, are a uniquely challenging environment for the deployment of machine learning. The tiny energy budgets of these devices lie beyond what is feasible for conventional deep neural networks, particularly in high-throughput scenarios, requiring us to rethink how we approach edge inference. In this work, we propose ULEEN, a model and FPGA-based accelerator architecture based on weightless neural networks (WNNs). WNNs eliminate energy-intensive arithmetic operations, instead using table lookups to perform computation, which makes them theoretically well-suited for edge inference. However, WNNs have historically suffered from poor accuracy and excessive memory usage. ULEEN incorporates algorithmic improvements and a novel training strategy inspired by binary neural networks (BNNs) to make significant strides in addressing these issues. We compare ULEEN against BNNs in software and hardware using the four MLPerf Tiny datasets and MNIST. Our FPGA implementations of ULEEN accomplish classification at 4.0–14.3 million inferences per second, improving area-normalized throughput by an average of 3.6× and steady-state energy efficiency by an average of 7.1× compared to the FPGA-based Xilinx FINN BNN inference platform. While ULEEN is not a universally applicable machine learning model, we demonstrate that it can be an excellent choice for certain applications in energy- and latency-critical edge environments.

FPGA implementation of high performance image de-noising filter

FPGA implementation of high performance image de-noising filter

Real Time FPGA Implementation of an Efficient High Speed Harris Corner Detection Algorithm Based on High-Level Synthesis

Computer vision systems use corner detection to identify features in an image. In applications such as motion detection, tracking, picture registration, and object recognition, corner detection is often one of the initial steps. In this paper, a real-time image processing system based on Harris corner detection was designed and implemented using Zynq architecture and model-based design tools. The system was based on a development board containing the Zynq-7000 chip, which consists of a combination of FPGA and microprocessor, and the image taken with a high-resolution camera was processed in real-time by applying color conversion and Harris corner detection. The filter hardware designs used in the system were made using the HDL Coder tool in Matlab/Simulink without writing HDL code. The hardware that receives images from the camera was designed on a model-based basis with the Xilinx Vivado 2020. The HDL code that was implemented on the Xilinx ZedBoard using Vivado software was then validated to ensure real-time operation with the incoming video stream. The results achieved exhibited superiority compared to prior implementations in terms of area efficiency (reduced number of gates on the target FPGA) and speed performance on an identical target card. Using the rapid prototyping approach, two alternative hardware accelerator designs were created using various high-level synthesis tools. This design used less than 50% of the host FPGA's logic resources and was at least 30% faster than current implementations.

FPGA Implementation of High-Performance Truncated Rounding based Approximate Multiplier with High-Level Synchronous XOR-MUX Full Adder

In research and development, the most emerging field in digital signal processing and image processing is rounded-based approximated signed and unsigned multipliers. In the present research, we propose some cutting-edge, Preformation, and logic simplification technology connected to processing the Discrete cosine transform (DCT) and Discrete wavelet transform (DWT) images for sharpening. This technology will yield a truncated shifter incorporated with logical XOR-MUX Full adder techniques. A reliable and cost-effective approximate signed and unsigned multiplier was created for the rounding method. While this more advanced technology includes many approximate multipliers, it sacrifices the ability to find the closest integer of a rounded value when combining signed and unsigned capabilities, resulting in higher absolute errors than other approximate multipliers based on rounding. This proposed work will introduce a novel method of Truncated Shifter Rounding-based Approximate Multiplier integrated with a High-Level Synchronous XOR-MUX Full Adder design to minimize the number of logic gates and power consumption in the multiplier architecture. The Truncated RoBA (Rounding-based Approximate Multiplier) with XOR MUX Full Adder will reduce the logic size in the shifter and the arithmetic circuit. The work will modify this rounding-based approximate multiplier to minimize area, delay, and power consumption. This proposed architecture will be integrated with two fundamental changes: firstly, its Barrel shifter method will be replaced with a truncated shifter multiplier with XOR MUX Full Adder, and secondly, the parallel prefix Brent Kung adder will be replaced with a carrying-save adder with XOR MUX Full Adder. Finally, this architecture was designed using Verilog-HDL and synthesized using the Xilinx Vertex-5 FPGA family, targeting the device Xc7Vx485tFFg1157-1. It resulted in a reduction of area LUT (34%), power (1%), delay (32%), and error analysis (75%) when compared to the existing RoBA.

FPGA Implementation of Metaheuristic Optimization Algorithm

Metaheuristic algorithms are gaining popularity amongst researchers due to their ability to solve nonlinear optimization problems as well as the ability to be adapted to solve a variety of problems. There is a surge of novel metaheuristics proposed recently, however it is uncertain whether they are suitable for FPGA implementation. In addition, there exists a variety of design methodologies to implement metaheuristics upon FPGA which may improve the performance of the implementation. The project begins by researching and identifying metaheuristics which are suitable for FPGA implementation. The selected metaheuristic was the Simulated Kalman Filter (SKF) which proposed an algorithm that was low in complexity and used a small number of steps. Then the Discrete SKF was adapted from the original metaheuristic by rounding all floating-point values to integers as well as setting a fixed Kalman gain of 0.5. The Discrete SKF was then modeled using behavioral modeling to produce the Binary SKF which was then implemented onto FPGA. The design was made modular by producing separate modules that managed different parts of the metaheuristic and Parallel-In-Parallel-Out configuration of ports was also implemented. The Discrete SKF was then simulated on MATLAB meanwhile the Binary SKF was implemented onto FPGA and their performance were measured based on chip utilization, processing speed, and accuracy of results. The Binary SKF produced speed increment of up to 69 times faster than the Discrete SKF simulation.

Enhancing TCP via Hysteresis Switching: Theoretical Analysis and Empirical Evaluation

In this paper we study the relationship between the TCP packet loss cycle and the performance of time-sensitive traffic in data centers. Using real traffic measurements and analysis, we find that such loss cycles are not long enough to enable most partition-aggregate time-sensitive TCP applications to recover their packet losses via the TCP 3-dup ACKs mechanism. As a result, the Timeout (RTO) mechanism is frequently triggered, leading to the expansion of the flow completion times (FCT) of such applications by orders of magnitude. Hence, we seek an alternative method that does not change the virtual machines and that can effectively expand the loss cycle duration to enable short flows to finish their transfer without incurring the cost of the RTO. To this end, we propose a novel TCP-AQM mechanism that alternates between a slow constant bitrate (CBR) mode and a fast TCP rate via hysteresis switching to expand the loss cycle. We prove the stability of the proposed TCP-AQM via a control theoretic model, then evaluate its performance gains via small and large scale NS2 simulation and by real FPGA implementation of a prototype on the NetFPGA platform. The results show considerable improvements in FCT distribution and reduction of missed deadlines in simulation and real experiments.

Parallel Doubly Fed Symbol Timing Recovery Algorithm and FPGA Implementation for Burst Broadband Satellite Access

Parallel Doubly Fed Symbol Timing Recovery Algorithm and FPGA Implementation for Burst Broadband Satellite Access

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

In this article, a low-complexity VLSI architecture based on a radix-4 hyperbolic COordinate Rotion DIgital Computer (CORDIC) is proposed to compute the N{{rm th}} root and N{{rm th}} power of a fixed-point number. The most recent techniques use the radix-2 CORDIC algorithm to compute the root and power. The high computation latency of radix-2 CORDIC is the primary concern for the designers. N{{rm th}} root and N{{rm th}} power computations are divided into three phases, and each phase is performed by a different class of the proposed modified radix-4 CORDIC algorithms in the proposed architecture. Although radix-4 CORDIC can converge faster with fewer recurrences, it demands more hardware resources and computational steps due to its intricate angle selection logic and variable scale factor. We have employed the modified radix-4 hyperbolic vectoring (R4HV) CORDIC to compute logarithms, radix-4 linear vectoring (R4LV) to perform division, and the modified scaling-free radix-4 hyperbolic rotation (R4HR) CORDIC to compute exponential. The criteria to select the amount of rotation in R4HV CORDIC is complicated and depends on the coordinates X^j and Y^j of the rotating vector. In the proposed modified R4HV CORDIC, we have derived the simple selection criteria based on the fact that the inputs to R4HV CORDIC are related. The proposed criteria only depend on the coordinate Y^j that reduces the hardware complexity of the R4HV CORDIC. The R4HR CORDIC shows the complex scale factor, and compensation of such scale factor necessitates the complex hardware. The complexity of R4HR CORDIC is reduced by pre-computing the scale factor for initial iterations and by employing scaling-free rotations for later iterations. Quantitative hardware analysis suggests better hardware utilization than the recent approaches. The proposed architecture is implemented on a Virtex-6 FPGA, and FPGA implementation demonstrates 19% less hardware utilization with better error performance than the approach with the radix-2 CORDIC algorithm.

FPGA Hardware Acceleration Research and Implementation of Deep Learning Algorithms

The convolutional neural network model is an important algorithm for deep learning, and YOLOv3-tiny based on this model has excellent object detection ability. However, the computational power required by the model is still large, and it is difficult to realize the application in the embedded field. This paper proposes a hardware acceleration method for YOLOv3-tiny and implements it on FPGA platform. Firstly, the fixed-point quantitative processing was carried out for the network, and an appropriate fixed-point strategy was designed with the data accuracy as the index. Secondly, the parallel computing design and pipeline optimization principle were carried out, and the FIFO structure was introduced to shorten the running time. Finally, the experiment was carried out on the Xilinx PYNQ-Z2 platform, and the data were compared with the previous related work.

Provisional Microgrid Frequency Regulation by Brain Emotional Learning Based Intelligent Controller and Implementation Through FPGA

With the advancement of technology and human movement towards evolution, intelligent control methods are becoming more important. One of the areas of progress is related to the development of new frameworks for electricity generation and distribution systems, and the microgrid structure with economic capabilities is one of the frameworks. Accordingly, this paper presents a new practical method for controlling the frequency of microgrids and is able to cover the following issues at the same time. 1- It considers the nonlinear model of provisional microgrid which has a hybrid structure (AC and DC) in addition to renewable energy sources. 2- Introduces a method for microgrid frequency control under different operational conditions that performs based on the brain emotional learning. 3- Ensures the operation and applicability of the control method for the provisional microgrid through implementation of FPGA for the first time 4- Confirms the robustness of the proposed method under extreme load changes. So, in the simulation scenarios, the effects of wind turbine and solar energy are considered and under the influence of various changes in load and system uncertainties, the robustness and efficiency of the proposed method are well demonstrated.

Dynamical investigation and FPGA implementation of a new Heartbeat model based on the Barrio-Varea-Aragon-Maini oscillator

This paper is devoted to the investigation of the nonlinear dynamics of a heartbeat model. The model is based on three coupled nonlinear autonomous oscillators representing the three automatism centres of the physical heart; each of these automatism centres is represented by an autonomous Barrio-Varea-Aragon-Maini (BVAM) oscillator model. Our study includes theoretical and experimental investigations. The theoretical part consists of the analysis of fixed point(s), bifurcations, Hamiltonian energy, hysteretic behaviour and coexisting attractors. The experimental investigation includes the discretization of the mathematical model followed by its synthesis and implementation under the Vivado 2017.4 platform and its simulation and its physical implementation on the Nexys-4 Artix-7 xc7a-100T FPGA trainer board. Two R-2R network digital-to-analog converters are built to visualise the practical results on a digital storage oscilloscope; a perfect correlation is observed between the theoretical, numerical and experimental results.

FPGA implementation of memristive Hindmarsh–Rose neuron model: Low cost and high-performing through hybrid approximation

Recent memristive neuron models have improved the ability of researchers to describe the operation of biological neurons. We employ FPGA implementation for a memristive neuron model, FPGA implementation provides an improved hardware system for mimicking brain behavior, and provides a better understanding of neurological phenomena. In this manuscript, a memristive Hindmarsh–Rose neuron model taking into account the influence of electromagnetic radiation and two multiplierless approximations of this model are presented. These approximations are piecewise linear (PWL) model and hybrid model, which mimic the behaviors of the original model. In the hybrid model, power 2-based approximation and a novel approximation are used simultaneously. The proposed models were subjected to error analysis, revealing that the PWL model exhibited mean NRMSEs of 3.56% and 2.3% for bursting and spiking modes, respectively. On the other hand, the hybrid model displayed mean NRMSEs of 1.92% and 1.34% for bursting and spiking modes. According to the FPGA implementation results, the PWL model yields the overall resources saving of 75.82% and 47.8% speed-up. But in the hybrid model, by optimizing the approximation functions, in addition to obtaining higher accuracy, better results are provided with a 67.3% improvement in the maximum frequency and the 78.64% saving in hardware resources.

Integration of Home Automation and Security System Controller with FPGA Implementation

A home automation system is essential for promoting a safe and comfortable living environment and notable energy conservation for the user. However, the system’s favour had been obstructed by cost, power usage, inadequate security, complexity, and no emergency backup power. Current home automation systems with controllers were limited by their number of ports, fixed architecture, non-durable and non-parallel executions. Keeping this in view, integration of home comfort system, security system, and the automatic load transfer switch features are proposed using the base of Cyclone IV E: EP4CE115F29C7 FPGA Board (DE2-115). The top-level module is developed via Verilog Hardware Descriptive Language (HDL) with the bottom-up technique and used test bench for functional verification via ModelSim-Altera. The PWM method was applied to the lighting system to control the dimming of light through its digital signals via a maximum 500000 counter to improve energy efficiency for the proposed design. In this project, 200Hz pulses are successfully simulated to prevent visible flickering of lights in duty cycle generation. The light intensity of 40% and 100% are verified and successfully generated according to the inputs provided by the status of the LDR sensor and IR sensor. The proposed controller gives correct corresponding outputs to the 13 actuators based on the detected input stimuli. The proposed design utilized a total of 162 (<1%) logic elements, 32 registers, and total pins of 74 (14%). The proposed design successfully integrated the three-sub module and provided control on comfort and security system operations to prevent service failure during power blackout conditions at the top-level and utilized a low ratio of the FPGA.

A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs

Numerous threats are associated with the globalized integrated circuit (IC) supply chain, such as piracy, reverse engineering, overproduction, and malicious logic insertion. Many obfuscation approaches have been proposed to mitigate these threats by preventing an adversary from fully understanding the IC (or parts of it). The use of reconfigurable elements inside an IC is a known obfuscation technique, either as a coarse grain reconfigurable block (i.e., eFPGA) or as a fine grain element (i.e., FPGA-like look-up tables). This paper presents a security-aware CAD flow that is LUT-based yet still compatible with the standard cell based physical synthesis flow. More precisely, our CAD flow explores the FPGA-ASIC design space and produces heavily obfuscated designs where only small portions of the logic resemble an ASIC. Therefore, we term this specialized solution a “hybrid ASIC” (hASIC). Nevertheless, even for heavily LUT-dominated designs, our proposed decomposition and pin swapping algorithms allow for performance gains that enable performance levels that only ASICs would otherwise achieve. On the security side, we have developed novel template-based attacks and also applied existing attacks, both oracle-free and oracle-based. Our security analysis revealed that the obfuscation rate for an SHA-256 study case should be at least 45% for withstanding traditional attacks and at least 80% for withstanding template-based attacks. When the 80% obfuscated SHA-256 design is physically implemented, it achieves a remarkable frequency of 368MHz in a 65nm commercial technology, whereas its FPGA implementation (in a superior technology) achieves only 77MHz.