FPGA Implementation Research Articles

Design and FPGA Implementation of Pre-computation Based Radix-4 Hyperbolic CORDIC for Direct Digital Synthesis

Design and FPGA Implementation of Pre-computation Based Radix-4 Hyperbolic CORDIC for Direct Digital Synthesis

Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming

In this brief, we propose a FPGA implementation of a novel Variable Fractional Delay (VFD) filter architecture for digital wideband (hundred of MHz or more) beamforming applications. The proposed architecture is based on a multirate structure that allows reaching high performance in terms of amplitude and group delay with a significant reduction in design complexity. Usually, the antenna’s beams are modified by introducing precise delays that can be multiples or fractions of the sampling period. The most used structures for realizing this operation are Farrow filters but, for wideband applications, the classical Farrow structure may require a huge amount of resources. A common solution to simplify the Farrow filter architecture is interpolation. However, this solution requires an increase of the clock frequency which is not always possible. In this context, our multirate approach mitigates the limitations in terms of computational complexity avoiding the requirement to increase of the clock frequency, while still exhibiting great performance. A comparison between a reference design based on the proposed approach and the literature is also provided. The experimental results confirm that the proposed architecture, characterized by a computational complexity similar to other works, exhibits better performance without the need to increase the clock frequency.

FPGA Implementation of Flexible Successive-Cancellation Polar Decoder

Kanal kapasitesi, bir kanalın iletilebileceği maksimum bit hızını ifade eder. Kutupsal kodlar, simetrik ikili girişli, hafızasız kanallar için sonsuz blok uzunluğunda kanal kapasitesine erişebilen ilk hata düzeltme kodlarıdır. Kutupsal kodların bu başarımı ile 5. Nesil Yeni Radyo Haberleşme standardında kullanımına karar verilmiştir. Bu çalışmada, farklı blok uzunluklarında ve farklı kod oranlarında kutupsal kodların, ardışık-çıkarım (successive-cancellation) kod çözücü algoritması alanında programlanabilir kapı dizileri (Field-programmable gate array, FPGA) ile gerçeklemesi anlatılmıştır.

FPGA Implementation of Parameter-Switching Scheme to Stabilize Chaos in Fractional Spherical Systems and Usage in Secure Image Transmission

The main objective of this work was to implement the parameter-switching chaos control scheme for fractional-order spherical systems and develop a chaos-based image encryption and transmission system. The novelty in the developed secure communication system is the application of the parameter-switching scheme in the decryption of RGB and grayscale images, which undergo one round of encryption using the chaotic states of the fractional system and a diffusion process. The secure communication system has a synchronized master and slave topology, resulting in transmitter and receiver systems for encrypting and decrypting images, respectively. This work was demonstrated numerically and also implemented on two FPGAs, namely Artix-7 AC701 and Cyclone V. The results show that the parameter-switching scheme controls chaos in the fractional-order spherical systems effectively. Furthermore, the performance analysis of the image encryption and transmission system shows that there is no similarity between the original and encrypted images, while the decryption of the encrypted images is without a loss of quality. The best result in terms of the encryption was obtained from the chaotic state x of the fractional-order system, with correlation coefficients of 0.0511 and 0.0392 for the RGB and grayscale images, respectively. Finally, the utilization of the FPGA logical resources shows that the implementation on Artix-7 AC701 is more logic-efficient than on Cyclone V.

A deep learning-based side channel attack model for different block ciphers

Recently, there has been renewed interest in the combination of deep learning and side-channel analysis (SCA). Many previous studies have transformed the traditional SCA into a classification problem in deep learning. This paper considers it as a regression problem based on the principle that the changes of some circuit states are related to the special operation in cipher. We proposed a regression model which consists of an initial layer, a deep feature mining dense layer, and a regression layer. In the term of dataset, there are two sources of data: the raw ASCAD power traces and the data sampled from FPGA implementation of AES and PRESENT. The mainly advantages of this model and regression task processing method is that it can adapt to different cryptographic algorithms on the same hardware device. Moreover, the experimental result that the model can significantly improve the attack accuracy of SCA. In ASCAD, its prediction accuracy achieves 2.90% and 3.63% for two different intermediate values, and their correlation coefficient evaluation 0.873, 0.840. In FPGA power dataset, their prediction and correlation coefficient are 3%, 4%, and 0.963, 0.987 respectively.

A family of new generalized multi-scroll Hamiltonian conservative chaotic flows on invariant hypersurfaces and FPGA implementation

A family of new generalized multi-scroll Hamiltonian conservative chaotic systems(HCCSs) are firstly found by investigating Hamiltonian energy of a Hamiltonian conservative chaotic system. And the novelty of the family of new generalized multi-scroll HCCSs is that they are on some invariant hypersurfaces depending on Hamiltonian energy. Subsequently, some numerical analysis are given to show multi-scroll chaotic dynamics and complex characteristics of the family of new generalized multi-scroll HCCSs. Finally, FPGA circuits are employed to implement the family of new generalized multi-scroll HCCSs, which not only physically show the existence of multi-scroll dynamics, but also provide a family of new pseudo-random signal generators for engineering applications.

FPGA Implementation for Elliptic Curve Cryptography Algorithm and Circuit with High Efficiency and Low Delay for IoT Applications.

The Internet of Things requires greater attention to the security and privacy of the network. Compared to other public-key cryptosystems, elliptic curve cryptography can provide better security and lower latency with shorter keys, rendering it more suitable for IoT security. This paper presents a high-efficiency and low-delay elliptic curve cryptographic architecture based on the NIST-p256 prime field for IoT security applications. A modular square unit utilizes a fast partial Montgomery reduction algorithm, demanding just a mere four clock cycles to complete a modular square operation. The modular square unit can be computed simultaneously with the modular multiplication unit, consequently improving the speed of point multiplication operations. Synthesized on the Xilinx Virtex-7 FPGA platform, the proposed architecture completes one PM operation in 0.08 ms using 23.1 k LUTs at 105.3 MHz. These results show significantly better performance compared to that in previous works.

Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer

This paper studies small to medium-sized monolithic switches for FPGA implementation and presents a novel switch design that achieves high algorithmic performance and FPGA implementation efficiency. Crossbar switches based on virtual output queues (VOQs) and variations have been rather popular for implementing switches on FPGAs, with applications in network switches, memory interconnects, network-on-chip (NoC) routers etc. The implementation efficiency of crossbar-based switches is well-documented on ASICs, though we show that their disadvantages can outweigh their advantages on FPGAs. One of the most important challenges in such input-queued switches is the requirement for iterative scheduling algorithms. In contrast to ASICs, this is more harmful on FPGAs, as the reduced operating frequency and narrower packets cannot “hide” multiple iterations of scheduling that are required to achieve a modest scheduling performance.Our proposed design uses an output-queued switch internally for simplifying scheduling, and a queue balancing technique to avoid queue fragmentation and reduce the need for memory-sharing VOQs. Its implementation approaches the scheduling performance of a state-of-the-art FPGA-based switch, while requiring considerably fewer resources.

Multistage FPGA Least Mean Squares Filters Suppressing Multiple Narrowband Radio-Frequency Interferences in the Radio Detection of Cosmic Rays

The article presents the FPGA implementation of 256- and 768-stage Least Mean Squares filters with rectangular, Hamming and Kaiser windows to suppress at least 10 narrow-bands RFIs. The analysis shows extremely high efficiency Radio Frequency Interference (RFI) elimination. 9-bit real cosmic ray data from the Auger Engineering Radio Array (AERA) was used as patterns and mixed with 14-bit multiple narrow-band RFIs. They were hidden deep within RFI’s background. After the cleaning process, the patterns were brought out and are practically without contamination.

FPGA Implementation of Associative Processors

In order to deal with increasingly complex computing problems, an In-memory-based computation system was proposed to replace the traditional Von-Neumann architectures. In-memory computing can save the time and energy of data movement between the memory and processor to avoid the memory-wall bottleneck of traditional Von-Neumann architecture. The associative processor (AP) is such an architecture that is proposed to implement in-memory computing. Content addressable memory (CAM), as a critical part of in-memory computing, plays an important role in an AP. In this paper, we proposed a novel FPGA implementation of the AP, including the CAM and its peripheral circuits, such as the controller, data cache, instruction cache, and program counter. The design details of the whole AP architecture are described by Verilog HDL. To the best of our knowledge, this is the first work that implements an associative processor on a real-world FPGA platform.

Oversampling Techniques to Improve the Accuracy of Hardware-in-the-Loop Switching Models

Real-time Hardware-In-the-Loop implementations for power converters involve digital sampling of the on-off signals that are applied to the switches. The most basic way of considering it, is to process only one switch state during a simulation step. This usually causes an incorrect input reading because it can change during the step. The negative effects include the appearance of undesirable subharmonics and numerical inaccuracy. In this work, input signal oversampling is proposed. Thus, several switch states can be properly processed within the same simulation step. The question is how to use this additional information. This paper proposes two oversampling approaches: a sequential one, which is based on previous works, and a parallel implementation, which is the main contribution of the paper. The results obtained with these techniques are compared between them and with the model without oversampling, showing a significant increase in accuracy for both oversampling approaches around 98%. Although the accuracy is very similar in both methods, synthesis results for FPGA implementation are clearly better for the parallel method, which can be easily adapted to process multiple switching events. The final experimental results show a great subharmonic decrease up to 99%.

FPGA Implementation of Medical Image Fusion

FPGA Implementation of Medical Image Fusion

FPGA Implementation of an Adaptive Equalizer with TLBO and PSO Variant

This paper presents the hardware implementation of two algorithms, Particle Swarm Optimization with Time Varying Inertia Weight and Teaching Learning-Based Optimization, which are applied to an Adaptive Equalizer with a Field Programmable Gate Array. Before the hardware implementation, MATLAB simulation results are also presented with a parameter like mean square error. Error convergence graphs of two algorithms have been observed for signal-to-noise ratios 10, 20, and 30 dB. The frequency response of the channel, equalizer, and of cascaded system is also presented. After MATLAB simulation, the same algorithm is implemented on Field Programmable Gate Array and a complete analysis is presented based on different parameters, resource utilization, execution time, frequency, and power required. Register transfer level views and simulation waveforms are also presented. By overall observation from Software and Hardware results, it is observed that Teaching Learning-Based Optimization algorithm is giving a better performance than Particle Swarm Optimization with Time Varying Inertia Weight algorithm.

An Implicit Multidimensional Parity based Data Coding and Decoding Algorithms with FPGA Implementation in Communication Systems

An Implicit Multidimensional Parity based Data Coding and Decoding Algorithms with FPGA Implementation in Communication Systems

Energy balance via memristor synapse in Morris-Lecar two-neuron network with FPGA implementation

Synapses can regulate the energy balance in the neural network. In this work, a two-neuron network is established by coupling two Morris-Lecar neurons using a memristor synapse. The periodic/hyperchaotic spiking-bursting patterns in the two-neuron network are portrayed using bifurcation plot, phase portrait, and time-domain waveform. The asynchronous behaviors exhibited by the numerical results show the difference of the inner field energy of individual neurons. To investigate the biophysical mechanism in the two-neuron network, the Hamiltonian energy function of a single neuron is derived by Helmholtz's theorem to equivalently describe its inner field energy, and the bioelectric activities are analyzed in combination with synchronization error functions. It is revealed that the initial state of memristor synapse can regulate the energy diversity in the two-neuron network and achieve the energy balance in the transient state. Two neurons firing in hyperchaotic pattern exchange field energy through the memristor synapse as a coupling channel until energy balance and complete synchronization. In the complete synchronization state, the memristor synapse is silent, which leads to the retrograding of hyperchaotic firing behaviors. Finally, an FPGA-based digital electronic two-neuron network is developed, and the experimental measurements well confirm the numerical simulations of bioelectric activities.

Correction to: FPGA implementation of hardware accelerated RTOS based on real-time event handling

Correction to: FPGA implementation of hardware accelerated RTOS based on real-time event handling

Image lossless compression algorithm optimization and FPGA implementation

In this thesis, a minimum redundant prefix coding with higher compression ratio and lower time complexity is proposed for lossless compression of HD images. The compression algorithm is based on Canonical Huffman coding, preprocesses the data source to be compressed according to the image data features, and then compresses the data in batches using the locally uneven features in the data, which improves the compression ratio by 1.678 times compared with the traditional canonical Huffman coding. During the implementation of the algorithm, the counting sorting method with lower time complexity and the code-length table construction method without relying on binary trees are used to reduce the complexity of the algorithm and achieve the purpose of real-time data processing by the system. Finally, the proposed compression algorithm is deployed in FPGA to improve the encoding rate by parallel hardware circuit and pipeline design.

A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability

In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply voltage and temperature variations and measured performances have been compared against state-of-the-art PUFs from the literature. The comparison has shown that the proposed PUF implementation exhibits the best reliability performance while occupying the minimum FPGA resource usage achieved in the PUF literature.

PID-FUZZY Control System for Autonomous Underwater Vehicles (AUV): Highly Accurate FPGA Implementation

Because of the linear and nonlinear variations in the operating environment, autonomous underwater vehicles (AUVs) are one of the most difficult applications. The complexity of the control algorithm should be less for real-time implementation in a field programable gate array logic (FPGA) device. In this work, a highly accurate FPGA implementation of PID-Fuzzy control strategy is proposed for an AUV operation that is extremely precise. Parameters such as weight, water density, and depth are used to perform highly efficient and accurate control for the proposed system. A type II fuzzy logic controller and accompanying proportional-integral- derivative controller are used to confine pitch and depth boundaries. The proposed design is modeled using SIMULINK software, and Verilog code is generated using hardware description language coder from MATLAB. Xilinx software is used to synthesize the Verilog code for spartan FPGA. The proposed technique improves the accuracy and reduces the response time when compared to the conventional control strategy.

FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications.

Miniaturized calcium imaging is an emerging neural recording technique that has been widely used for monitoring neural activity on a large scale at a specific brain region of rats or mice. Most existing calcium-image analysis pipelines operate offline. This results in long processing latency, making it difficult to realize closed-loop feedback stimulation for brain research. In recent work, we have proposed an FPGA-based real-time calcium image processing pipeline for closed-loop feedback applications. It can perform real-time calcium image motion correction, enhancement, fast trace extraction, and real-time decoding from extracted traces. Here, we extend this work by proposing a variety of neural network based methods for real-time decoding and evaluate the tradeoff among these decoding methods and accelerator designs. We introduce the implementation of the neural network based decoders on the FPGA, and show their speedup against the implementation on the ARM processor. Our FPGA implementation enables the real-time calcium image decoding with sub-ms processing latency for closed-loop feedback applications.