FPGA Implementation Research Articles

Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks.

Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm2 and verifies the suitability of an on-chip ReSuMe learning algorithm implementation and its capability of integration with a multitude of external and already designed structures of Spiking Neural Networks (SNNs).

FPGA implementation of proposed number plate localization algorithm based on YOLOv2 (You Only Look Once)

FPGA implementation of proposed number plate localization algorithm based on YOLOv2 (You Only Look Once)

ASIC vs FPGA based Implementations of Built-In Self-Test

Linear Feedback Shift Registers (LFSRs) are play key role in testing of for Very Large Scale Integration (VLSI) Integrated Circuits (ICs) testing. Due to tremendous IC complex growth, testing of recent VLSI ICs technology have become more complicated. This led to develop a popular alternate viable solution in the form of Built-In Self-Test (BIST) technology as compared to Automatic Test Equipment (ATE). However, the challenges of BIST technology remain the subject of research. Furthermore, implementation of BIST’s LFSR on Application Specific Integrated Circuit (ASIC) versus Field Programmable Gate Array on (FPGA) platform is current area of research especially in context to power consumption. Hence, to make an informed choice between ASIC and FPGA for implementing BIST’s LFSR we focus on study of design of reconfigurable LFSR on ASIC versus FPGA platform. The Electronic Design Automation (EDA) tool, Cadence is used for implementing BIST’s LFSR on ASIC platform. Whereas, Hardware Description Language (HDL), Verilog is used to implement BIST’s LFSR on FPGA platform. During experimental methodology, maximum frequency, the critical path delay is investigated to assess the power dissipation. The functional and timing simulation models are used to verify the implemented reconfigurable BIST’s LFSR designs. The obtained results show that the performance, in terms of speed and power, of ASIC implementation is far better than traditional FPGA implementation.

A High Performance and Robust FPGA Implementation of a Driver State Monitoring Application.

A high-performance Driver State Monitoring (DSM) application for the detection of driver drowsiness is presented in this paper. The popular Ensemble of Regression Trees (ERTs) machine learning method has been employed for the alignment of 68 facial landmarks. Open-source implementation of ERTs for facial shape alignment has been ported to different platforms and adapted for the acceleration of the frame processing speed using reconfigurable hardware. Reducing the frame processing latency saves time that can be used to apply frame-to-frame facial shape coherency rules. False face detection and false shape estimations can be ignored for higher robustness and accuracy in the operation of the DSM application without sacrificing the frame processing rate that can reach 65 frames per second. The sensitivity and precision in yawning recognition can reach 93% and 97%, respectively. The implementation of the employed DSM algorithm in reconfigurable hardware is challenging since the kernel arguments require large data transfers and the degree of data reuse in the computational kernel is low. Hence, unconventional hardware acceleration techniques have been employed that can also be useful for the acceleration of several other machine learning applications that require large data transfers to their kernels with low reusability.

Probabilistic Principle Component Analysis based Feature Extraction of Embedded System Applications with Deep Neural Network based Implementation in FPGA

The study of hardware and software systems is of major are very important advent in new devices for communication and progress in system of security. In fast pace mobile and embedded devices application in every day’s life leads some new emerging area for research in data mining field. In this we have some technologies which have demand and error free using the principle of component of PPCA. For Embedded system the applications of PCA is basically applied initially for the lessen the having different qualities especially being to simple of the data. PPCA which have the updated version of PCA which is surveyed by similarity measure. In this work, experiments are extensively carried out, using a FPGA based light weight cryptographic data set having benchmark set to check and illustrate the viability, competence, litheness which are reconfigurable embedded system which are having data mining . Which have FPGA are reconfigurable for the computing architectures for hardware and in neural network. FPGA using the multilayer Cascaded for neural network which are forward in nature (CFFNN) and Deep Neural Network also called as DNN with a huge neuron is still a thought-provoking task. This shortcoming leads to elect the FPGA capacity for a particular application we have used the method of implementation which has two neural network have been implemented and compared , namely, CFFNN and DNN. It can be shown that for reconfigurable embedded system, PPCA based data mining and Machine learning based realization can give more speed up less iteration and more space savings when we have compared it with the static conventional version.

Area‐time efficient point multiplication architecture on twisted Edwards curve over general prime field GF(p)

AbstractElliptic curve point multiplication is the main primitive required in almost all security schemes using elliptic curve cryptography (ECC). It is the leading computationally intensive operation that sets the overall performance of the associated cryptosystem. This work presents a highly novel area–time efficient elliptic curve point multiplier over a general prime field . It is based on an efficient radix‐23 parallel multiplier, which performs a ‐bit multiplication in clock cycles. On the system level, the twisted Edwards curves with unified point addition using projective coordinates are adopted, where an efficient scheduling technique is presented to schedule several operations on deployed modular arithmetic units. Due to the introduced optimization at different stages of the design, latency, hardware resource requirement, and total clock cycle count are reduced significantly. Synthesis, and implementation of the proposed design over different Xilinx FPGA platforms are completed using the Xilinx ISE Design Suite tool for key sizes of 192, 224, and 256 bits. The 256‐bit Xilinx Virtex‐7 FPGA implementation reveals that it completes a single point multiplication operation in 0.8 ms and occupies 6.7K FPGA slices in a clock cycle count of 132.2K. It produces significantly better area–time product and throughput per slice than the contemporary designs. The proposed design also has the potential to counter simple power analysis and timing attacks. Thus, it is an elegant solution to develop ECC‐based cryptosystems for applications, where both speed and hardware resource consumption are important.

Flexible FPGA 1D DCT hardware architecture for HEVC

In this work, we propose a flexible 1D DCT hardware design with a constant throughput of 32 pixels per cycle for all transform block (TB) size modes. The design supports all TB sizes defined in the HEVC standard. Flexibility is achieved by multiplexing only the outputs, which results in lower data path delays compared to other proposed designs. Also, the additional partial butterfly units are transferred to the output of transformation cores. The transformation operation is done in a single stage to minimize the latency of the design and reduce hardware usage. The highly parallel input reduces the need for a very high operational frequency, which is suitable for low-power FPGA designs. Four different reusable transformation cores are used that are designed using parallel Multiple Constant Multiplication (MCM) units to further reduce the calculation time. The design was implemented on the Virtex UltraScale + device. The implementation has hardware usage of 21,818 LUTs, and it can reach the maximal throughput of 4.90 Gsps at the working frequency of 153 MHz which is enough to support the video resolutions of up to 8192 × 4320@60fps. Comparison with the other works shows that DCT FPGA implementation without DSPs can reach the performance of the ASICs with trade-offs in power consumption.

Implementation of FPGA based real-time digital DAQ for high resolution, and high count rate nuclear spectroscopy application

This paper investigates a digital system for real-time nuclear data (pulse) analysis based on a field programmable gate array and a computer-based data acquisition software for high count rate and high-resolution spectroscopy applications. A novel FPGA-based design is proposed with enhanced universality for real-time energy spectroscopy applications encompassing gamma and charged particles in noisy environments. This design implements an adaptive digital pre-filter for noise reduction without distorting the preamplifier pulse shape for improvement in energy resolution. This adaptive approach can be used for a wide range of input pulses with varying rise and fall times without deteriorating the signal-to-noise ratio. The design incorporates a digital trapezoidal filter with a triggerless peak detection algorithm for improvement in energy resolution. A high-speed dual clock first-in-first-out memory is implemented for handling high data rates. The real-time analysis of the FPGA internal signals and nuclear spectroscopy experiments with high count rate have been carried out with random nuclear pulses using an emulator. The results have been compared with conventional VERSA-Module Euro data acquisition system and CR_RC based digital pulse processing approaches.

FPGA Implementation of 5G NR LDPC Codes

FPGA Implementation of 5G NR LDPC Codes

A fog-based anonymous authentication scheme with location privacy for wireless body area network with FPGA implementation

A fog-based anonymous authentication scheme with location privacy for wireless body area network with FPGA implementation

VECTOR-LOGICAL FAULT SIMULATION

Context. The main idea is the creation of vector-logical in-memory computing (VLC), which uses only read-write transactions on the address memory for faults-as-addresses simulation. There is no traditional logic. VLC is free from processor commands and ALU for computing organization and is therefore focused on implementation in SoC and FPGA. A vector-logical method of deductive matrix synthesis for the transportation of input faults, which has a quadratic computational complexity, is proposed. An inmemory simulator-automata for vector-deductive faults-as-addresses simulation, which based on read-write transactions for implementation in SoC is proposed. Objective. Development of a vector deductive method of fault simulation based on primitive read-write transactions for the analysis of logic circuits. Method. An input test set and a logical functionality vector are used. The proposed method is a development of the deductive vectors’ synthesis algorithm based on the truth table. The deductive matrix is intended for the synthesis and verification of tests using parallel simulation of faults-as-addresses combinations, based on read-write transactions over bits of deductive vectors in memory. Results. A vector method of the deductive matrices synthesis for the transportation of input faults vectors to the output of the element, was proposed. Data structures have been developed for parallel faults simulation of digital circuits based on a primitive readwrite transaction in matrix memory, where combinations of faults serve as address-columns. A sequencer of five blocks, that constitute a vector-logic computing, connected with deductive faults simulation based on read-write transactions, is proposed. Verification of models and methods on test examples has been performed. Conclusions. The scientific novelty consists in the development of the following innovative solutions: 1) a vector-logic method of synthesis of the deductive vectors matrix for parallel simulation of combinations of input faults-as-addresses, is proposed for the first time; 2) an automata for vector-deductive faults-as-addresses simulation, on the basis of read-write transactions, which is oriented for implementation in FPGA LUT, embedded online simulator SoC, as a core for faults simulation of RTL-level digital systems, was proposed for the first time; 3) the demonstration of the technological advantages of the vector-logic synthesis of deductive matrices is performed on numerous examples of traditional and RTL-logic, which accentuate the manufacturability of vectors in comparison with analytical deductive formulas during simulators construction; 4) a matrix of deductive vectors, as a set of vectorcolumns of Boolean derivatives is used to construct minimal tests for logical elements; 5) the recursive formula for the synthesis of the permutation of coordinates matrix in the logical activity vector makes it possible to significantly simplify the obtaining of the deductive matrix for faults-as-addresses simulation. The practical significance lies in the fact that the in-memory simulator will allow to obtain the speed of faults simulation of real digital blocks for SoC at the level of hundreds of nanoseconds. Complexity estimates of the corresponding algorithms are given.

FPGA Centric Attention Based Deep Learning Network Evoked Chaotic Encryption to Mitigate Side Channel Attacks

Security concerns are growing, especially in applications where sensitive information is sent (such as health care devices, credit cards, and even Internet of Things (IoT) nodes), even while these developments bring in a modern revolution. This is due to the constant scaling of technologies, which has now been incredibly useful for delivering the new trend of development in the numerous domains such as communications, semiconductors, health care, and automation. Even when cutting-edge standard encryption algorithms are used in smart devices, the principal threats, such as Side-Channel Attacks (SCA) and Correlation Power Analysis (CPA), increase the susceptibility of encrypted cipher text to attacks. In order to defend against side channel assaults, the usefulness of deep learning algorithms combined with chaotic principles is examined in this paper. Scroll Mapping (SM) and Attention-Evoked Long Short-Term Memory (AE-LSTM) are used in the proposed study to effectively safeguard sensitive data while consuming little power. The most promising advancements in terms of all security metrics and hardware capabilities for obtaining high-speed performances are shown by experimental findings on an FPGA implementation of a suggested framework.

BSAPM: BlockChain based secured authentication protocol for large scale WSN with FPGA implementation

According to state-of-the-art, several multiple base station-based authentication and key agreement protocols exist. Still, most of the protocols are computationally inefficient and suffer from several potential attacks. In this research work, we consider WSN architecture, where multiple base stations are located in a distributed way. After that, we proposed a blockchain-based authentication and key agreement protocol for establishing secure communication. This protocol utilizes a smart contract facility during the registration of the sensor node. Our work also stores records of the sensor node in blockchain network. Most importantly, we have verified the proposed protocol using FPGA implementation, which further confirms the correctness of the generated session keys. BSAPM is demonstrated in terms of security threats using the Scyther tool, and we have also shown formal security analysis using the Real-or-Random(ROR) model. The informal security analysis demonstrates the protection against security threats. BSAPM is better in terms of communication, computation overheads, and functionality features when compared to the related other competitive schemes.

Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis

The spectral correlation density (SCD) is an important tool in cyclostationary signal detection and classification. Even using efficient techniques based on the fast Fourier transform (FFT), real-time implementations are challenging because of the high computational complexity. A key dimension for computational optimization lies in minimizing the wordlength employed. In this article, we analyze the relationship between wordlength and signal-to-quantization noise in fixed-point implementations of the SCD function. A canonical SCD estimation algorithm, the FFT accumulation method (FAM) using fixed-point arithmetic, is studied. We derive closed-form expressions for SQNR and compare them at wordlengths ranging from 14 to 26 bits. The differences between the calculated SQNR and bit-exact simulations are less than 1 dB. Furthermore, an HLS-based FPGA design is implemented on a Xilinx Zynq UltraScale+ XCZU28DR-2FFVG1517E RFSoC. Using less than 25% of the logic fabric on the device, it consumes 7.7 W total on-chip power and has a power efficiency of 12.4 GOPS/W, which is an order of magnitude improvement over an Nvidia Tesla K40 graphics processing unit (GPU) implementation. In terms of throughput, it achieves 50 MS/sec, which is a speedup of 1.6 over a recent optimized FPGA implementation.

E$${^2}$$CSM: efficient FPGA implementation of elliptic curve scalar multiplication over generic prime field GF(p)

E$${^2}$$CSM: efficient FPGA implementation of elliptic curve scalar multiplication over generic prime field GF(p)

An FPGA Architecture for the RRT Algorithm Based on Membrane Computing

This paper investigates an FPGA architecture whose primary function is to accelerate parallel computations involved in the rapid-exploring random tree (RRT) algorithm. The RRT algorithm is inherently serial, while in each computing step there are many computations that can be executed simultaneously. Nevertheless, how to carry out these parallel computations on an FPGA so that a high degree of acceleration can be realized is the key issue. Membrane computing is a parallel computing paradigm inspired from the structures and functions of eukaryotic cells. As a newly proposed membrane computing model, the generalized numerical P system (GNPS) is intrinsically parallel; so, it is a good candidate for modeling parallel computations in the RRT algorithm. Open problems for the FPGA implementation of the RRT algorithm and GNPS include: (1) whether it possible to model the RRT with GNPS; (2) if yes, how to design such an FPGA architecture to achieve a better speedup; and (3) instead of implementing GNPSs with a fixed-point-number format, how to devise a GNPS FPGA architecture working with a floating-point-number format. In this paper, we modeled the RRT with a GNPS at first, showing that it is feasible to model the RRT with a GNPS. An FPGA architecture was fabricated according to the GNPS-modeled RRT. In this architecture, computations, which can be executed in parallel, are accommodated in different inner membranes of the GNPS. These membranes are designed as Verilog modules in the register transfer level model. All the computations within a membrane are triggered by the same clock impulse to implement parallel computing. The proposed architecture is validated by implementing it on the Xilinx VC707 FPGA evaluation board. Compared with the software simulation of the GNPS-modeled RRT, the FPGA architecture achieves a speedup of a 104 order of magnitude. Although this speedup is obtained on a small map, it reveals that this architecture promises to accelerate the RRT algorithm to a higher level compared with the previously reported architectures.

Bifurcation Analysis, Synchronization and FPGA Implementation of a New 3-D Jerk System with a Stable Equilibrium

This research paper addresses the modelling of a new 3-D chaotic jerk system with a stable equilibrium. Such chaotic systems are known to exhibit hidden attractors. After the modelling of the new jerk system, a detailed bifurcation analysis has been performed for the new chaotic jerk system with a stable equilibrium. It is shown that the new jerk system has multistability with coexisting attractors. Next, we apply backstepping control for the synchronization design of a pair of new jerk systems with a stable equilibrium taken as the master-slave chaotic systems. Lyapunov stability theory is used to establish the synchronization results for the new jerk system with a stable equilibrium. Finally, we show that the FPGA design of the new jerk system with a stable equilibrium can be implemented using the FPGA Zybo Z7-20 development board. The design of the new jerk system consists of multipliers, adders and subtractors. It is observed that the experimental attractors are in good agreement with simulation results.

Methodology for CNN Implementation in FPGA-Based Embedded Systems

The increasing interest in Convolutional Neural Networks (CNNs) is driving the study and design of different implementations for a variety of platforms, each intended to optimize performance, power consumption, or latency, according to the application’s needs. While GPUs have dominated the high-performance terrain, FPGAs have proved to be a promising alternative due to their relatively high performance, reduced power consumption and costs, compared with GPUs. The main concern regarding FPGA implementations lies in the effort needed to develop the systems and difficulties reusing or combining designs by different authors, due to the highly heterogeneous architectures used in each project. This work proposes a methodology and a high-level architecture designed for CNN implementations in FPGAs, that eases the development process, allows the reusability of designs, and helps to maximize performance, minimize latency, reduce resource utilization and avoid possible bottlenecks, while allowing high design flexibility. This proposal is validated by implementing a set of blocks that are later used to build different CNNs.

Feature-Based Scanning LiDAR-Inertial Odometry Using Factor Graph Optimization

Localization of a mobile robot in the absence of an absolute position sensor often relies on techniques such as visual or lidar-inertial odometry. While lidar has many advantages, the most capable sensors use scanning mechanisms, leading to motion-distorted scans. Previous strategies used to account for robot motion when performing state estimation and outlier rejection have drawbacks for use on highly dynamic, resource-constrained robots such as spacecraft during descent and landing. In this paper we develop a novel probabilistic factor for the inclusion of scanning lidar features, and an accompanying outlier rejection methodology. By using well-established, efficient feature tracking techniques, our image processing front end is both reliable and amenable to FPGA implementation, both of which are critical for operation on a spacecraft. We demonstrate our technique on a dataset from simulated planetary descent and landing. The results show that our system can be used to perform accurate lidar-inertial odometry, even in highly dynamic scenarios.

Efficient Implementation of Spontaneous Calcium Oscillations in the Central Nervous System on Reconfigurable Digital Boards

Biological systems in case of real-time state and also large-scale simulation approach are interesting and challenge-based due to different aspects of nonlinear mathematical modeling that can describe the interactions of biological blocks. Thus, hardware circuit designing of these basic blocks in the Central Nervous System (CNS) can be an important field in case of achieving high performance neuromorphic system emulator. This paper presents a high-speed, low-cost, and efficient digital circuit for emulating the plausible calcium-dynamic-based model of astrocyte which has spontaneous oscillations. The nonlinear high-cost functions of the complex astrocyte model are reformulated using the power-2 based low-cost terms using optimized exhaustive search algorithm. Subsequently, the proposed model is simulated in case of validating the presented model and new optimized functions. Finally, the proposed model is physically realized in hardware case using Virtex 4 FPGA platform to test and validate final circuits. FPGA implementation results confirmed the ability of the design to emulate biological cell behaviours in detail with high accuracy. The proposed hardware consumes maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\%$</tex-math> </inline-formula> of the all resources of a Virtex 4 board. Additionally, timing analysis and synthesize report represent that the proposed model works in a high frequency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm 371.56$</tex-math> </inline-formula> MHz. Moreover, to validate the results of implementation, the proposed model is compared with the original model and other similar works in terms of accuracy, speed-up, and maximum number of implemented astrocyte.