Impact Of Random Dopant Fluctuation Research Articles

Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET

This paper investigates the effect of random dopant fluctuation (RDF) on the performance of ferroelectric Germanium source vertical tunnel field effect transistor (FE GeS-vTFET) using 3-D device simulation. The variation in the on-state current (σION), off-state leakage current (σIOFF), current ratio σ(ION/IOFF), subthreshold swing (σSS), threshold voltage (σVTH), total gate capacitance (σCgg), transconductance (σgm) and cut-off frequency (σfT) for different source doping concentration and source thickness due to the effect of RDF are evaluated. The findings indicate an increasing tendency in RDF with higher doping concentration in the source region. The variation in the on-current is from 0.2173 mA to 0.2337 mA (∼1.075 times higher), and σIOFF varies from 4.939 fA to 16.545 fA (∼3.349 times higher) from 1 × 1020 /cm3 to 3 × 1020 /cm3 doping concentration, respectively for Germanium source thickness of 12 nm. RDF within the source region mainly contributes to the threshold voltage variation of about 92 % in all regions. The randomized dopant-induced σVTH for the FE GeS-vTFET compared with other field effect transistors of the same technology node showed a substantial reduction in σVTH, signifying that the device is more immune to the effects of RDF. Furthermore, the effect of temperature on the switching properties of the FE GeS-vTFET has been studied.

Increased Device Variability Induced by Total Ionizing Dose in 16-nm Bulk nFinFETs

This article investigates the device variability induced by the total ionizing dose (TID) effects in a commercial 16-nm bulk nFinFETs, using specially designed test structures and measurement procedures aimed at maximizing the matching between devices. DC static characteristic measurements show that below 100 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) the device variability is slightly affected by the total accumulated dose. However, when the total dose reaches 100 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ), the device variability increases significantly showing a correlation with pre-irradiation electrical responses of the devices. Transistors characterized by higher drain current exhibit the worst TID degradation. This phenomenon is likely due to the impact of random dopant fluctuations on the TID effects and/or to variations in the hydrogen concentration responsible for the TID-induced interface traps.

Reduction of Random Dopant Fluctuation-induced Variation in Junctionless FinFETs via Negative Capacitance Effect

In this study, we investigated the impact of random dopant fluctuation (RDF) on junctionless (JL) fin field-effect transistors (FinFETs) with ferroelectric (FE) negative capacitance (NC) effect. The RDF-induced variations were captured by using built-in Sano methodology in three-dimensional technology computer-aided design (TCAD) simulation. Compared to the regular JL-FinFETs, the variations in JL-FinFETs with NC effect (NCJL-FinFETs) was observed to be less via statistical Monte Carlo analysis, which further enhanced its performance as well. The evaluation and estimation of threshold voltage (V T ), ON-state current (I on ), OFF-state current (I off ), and subthreshold swing (SS) by different FE layer thicknesses indicated reduction in the standard deviations of V T (δV T ) and I on (δI on ) by 34.7% and 7.08%, respectively; the OFF-state current and its standard deviation shrank by approximately three orders of magnitude than the JL-FinFET counterpart. Although δSS was not monotonous, the SS was significantly improved to sub-60 mV/decade. To sum up, the regular JL-FinFETs containing the FE layer as NC effect not only improved the electrical performance, but also led to the resilience of the RDF-induced statistical variability.

Investigation of statistical variability in non-uniformly doped bulk junctionless FinFET

The impact of random dopant fluctuation (RDF), work function variation (WFV) and oxide thickness fluctuation (OTF) on the statistical variability of the electrical performance of non-uniformly doped bulk junctionless (JL) FinFET has been studied using three dimensional TCAD simulations. We illustrate that by specifying the appropriate doping profile in the bulk JL FinFET, enhanced statistical variability and electrical characteristics can be achieved. Numerically, it is indicated by values of standard deviation of device parameters, that the performance parameters of a uniformly doped bulk JL FinFET are seriously influenced by statistical variation compared to its non-uniformly doped counterparts.

Study of random dopant fluctuation in PNPN feedback FET

The impact of random dopant fluctuation (RDF) on the performance variation of a PNPN feedback field effect transistor (PNPN FBFET) is investigated using a 3D technology computer aided design tool. To investigate RDF-induced device performance variation (e.g. threshold voltage (VTH) variation), the nominal doping profile of each region in a PNPN FBFET is separately randomized. Consequently, in terms of RDF-induced VTH variation, the channel-2 region (i.e. gated channel region) plays a key role as a main contributor to VTH variation, as it is the most decisive region for determining gate-to-channel controllability. As an example, the value of σVTH resulting from the channel-2 region is nine times higher than that from the channel-1 region. Based on the simulation results, guidelines for variation-immune device design are comprehensively discussed.

Performance Improvements of Random Dopant Fluctuation-Induced Variability in Negative Capacitance MOSFETS

In this paper, we investigate the impact of random dopant fluctuation (RDF) on the statistical variations in negative capacitance MOSFETs (NCFETs) through a device simulation coupled with the Landau–Khalatnikov (LK) equation. Compact models for feedback mechanisms that are based on the internal gate voltage amplification in NCFETs are proposed. The results show that internal voltage amplification plays a decisive role in performance improvement of device variability. Further, our simulation study demonstrates that owing to the feedback mechanism, the dispersions of the performance parameters in NCFETs exhibit different statistical distribution characteristics compared to their MOSFET counterparts. Our study may provide further insight regarding device and/or circuit designs utilizing NCFETs.

Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With Metal–Interlayer–Semiconductor Source/Drain Contact Structure

The impact of random dopant fluctuation (RDF) on n-type Ge junctionless FinFETs (JLFETs) with metal–interlayer-semiconductor (MIS) source/drain (S/D) contact structure is firstly investigated via 3-D technology computer aided design (TCAD) simulations. The estimation and evaluation of standard deviations in threshold voltage (Vth), on-state current (Ion), off-state current (Ioff), subthreshold swing (SS), and drain induced barrier lowering (DIBL) by different Ge nanowire doping concentrations and different heights for RDF effects are performed. The results show a decreasing trend of RDF with lower doping concentration of the device. Furthermore, the influence of MIS S/D on RDF of n-type Ge JLFET is assessed through a comparative analysis between an n-type Ge JLFETs with and without MIS S/D structure. The analysis results estimate that MIS S/D can reduce performance variation to approximately 0.0237 V for ${\sigma }~\text{V}_{\mathrm{ th}}$ , 5.75 $\times \,\,10^{-5}$ A/ $\mu {\mathrm{ m}}$ for ${\sigma }~\text{I}_{\mathrm{ on}}$ , 4.30 $\times \,\,10^{-10}$ A/ $\mu {\mathrm{ m}}$ for ${\sigma }~\text{I}_{\mathrm{ off}}$ , 0.548 mV/dec for ${\sigma }$ SS, and 12.3 mV/V for DIBL, without severe performance degradation of the current nominal values. This estimation gives a significant insight on variability prediction of the 7 nm n-type Ge JLFET device with MIS S/D structure.

Device- and circuit-level variability due to random discrete dopant in resist- and spacer-defined nanoscale FinFETs

In current CMOS technology, parameter variations are playing a vital role in limiting the benefits of downscaling, especially in the nanodomain. This work presents the investigation of random dopant fluctuation (RDF) in several possible line-edge roughness (LER)-induced fin shapes of spacer- (i.e., correlated LER) and resist- (i.e., uncorrelated LER) defined patterning techniques for a 14-nm FinFET structure. The three-dimensional (3-D) technology computer-aided design simulation on a large statistical ensemble has been carried out to analyze the impact of the RDF on various device parameters such as threshold voltage, drive current, off current, and drain-induced barrier lowering. It is observed that the impact of RDF on electrical parameters mainly depends on the fin shape and is dominant in all resist-defined FinFET structures. It is also found that the impact of RDF can diminish significantly using the spacer-defined patterning technique. Further, the impact of RDF in spacer- and resist-defined FinFET structures has been investigated for noise margins of 6-T static random access memories (SRAM). It is concluded that random dopant variations in SRAM performance offer better immunity in the case of spacer-defined FinFETs compared with resist-defined FinFETs.

Effects of Device Scaling on the Performance of Junctionless FinFETs Due to Gate-Metal Work Function Variability and Random Dopant Fluctuations

This letter reports an investigation of the impact of device scaling on the performance of a junctionless FinFET due to gate-metal work function variability (WFV) and random dopant fluctuations (RDFs). Such investigation is made by using a 3-D numerical device simulator. Impacts of both WFV and RDF are found to increase with technology scaling when channel doping is also increased to meet the targeted $V_{T}/I_{\mathrm{\scriptscriptstyle OFF}}/I_{\mathrm{\scriptscriptstyle ON}}$ for the scaled technology nodes. Our investigations, however, suggest that the impact of RDF can be reduced significantly for scaled technology nodes if such target is met by keeping the channel doping unaltered and adjusting the gate-metal work function. This results in improved RDF-induced variability and deteriorated WFV-induced variability that in turn increases the relative impact of WFV for scaled technology nodes.

Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure

The impact of random dopant fluctuation (RDF) on a 10-nm n-type silicon (Si) FinFET with a metal-insulator-semiconductor (M-I-S) source/drain (S/D) structure is investigated using three-dimensional TCAD simulation. To determine the optimal aspect ratio of the fin for a variation-robust FinFET with an M-I-S S/D structure, various metrics for device performance are quantitatively evaluated. It is found that variation in RDF-induced threshold voltage (Vth) in the FinFET can be suppressed with a taller fin (i.e., a fin with a higher aspect ratio) because of better gate-to-channel controllability and wider channel width. For a fin aspect ratio (i.e., fin height to fin width) of 5.25:1, the standard deviation for RDF-induced Vth in a FinFET with an S/D doping concentration (NS/D) of 5 × 1020 cm−3 is 9.277 mV. In order to suppress RDF-induced Vth variation even further, an M-I-S structure with a heavily doped n-type ZnO interlayer can be introduced into the S/D region of the FinFET. For the tallest fin height, this M-I-S S/D structure (with an NS/D = 5 × 1019 cm−3) results in a standard deviation of 4.729 mV for RDF-induced Vth, while maintaining the on-state drive current (Ion) at a satisfactory level. Therefore, it is expected that a 10-nm n-type FinFET can be designed to be immune to Vth variation with the adoption of the proposed M-I-S S/D structure.

Enhancement of Transistor-to-Transistor Variability Due to Total Dose Effects in 65-nm MOSFETs

We studied device-to-device variations as a function of total dose in MOSFETs, using specially designed test structures and procedures aimed at maximizing matching between transistors. Degradation in nMOSFETs is less severe than in pMOSFETs and does not show any clear increase in sample-to-sample variability due to the exposure. At doses smaller than 1 Mrad( SiO 2 ) variability in pMOSFETs is also practically unaffected, whereas at very high doses-in excess of tens of Mrad( SiO 2 )-variability in the on-current is enhanced in a way not correlated to pre-rad variability. The phenomenon is likely due to the impact of random dopant fluctuations on total ionizing dose effects.

Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In0.53Ga0.47As GAA MOSFET

We investigate the impacts of random dopant (RD) and gate workfunction variability on the subthreshold characteristics of a 50-nm-gate-length inversion-mode gate-all-around In0.53Ga0.47As MOSFET using a 3-D finite-element quantum-corrected drift-diffusion device simulator calibrated to experimental data. We have studied threshold voltage, off-current, and subthreshold slope variations. The workfunction variations on the subthreshold characteristics dominate and decrease with the reduction in grain diameter. The simulated grain diameters of 10, 7, and 5 nm exhibit threshold voltage standard deviations of 52, 41, and 27 mV, respectively. These values are larger than those observed in TiN-metal-gate Si FinFETs for a similar gate length. The impact of RD fluctuations is negligible when compared with bulk Si MOSFETs, giving a threshold voltage spread of only 6 mV.

Study of Random Dopant Fluctuation Induced Variability in the Raised-Ge-Source TFET

The impact of random dopant fluctuations (RDF) on the performance of an optimized TFET design comprising a raised germanium (Ge) source region is investigated via 3-D TCAD simulation. The RDF within the source region results in degraded subthreshold swing and lower turn-on voltage for the raised-Ge-source TFET design. In addition, drain-induced barrier tunneling is mitigated with the raised source design. An optimized raised-Ge-source TFET is projected to provide for lower energy operation at frequencies up to 500 MHz when compared with an ideal MOSFET.

The potential of Fe-FET for robust design under variations: A compact modeling study

Semiconductor devices with self-feedback mechanisms are considered as a promising alternative to traditional CMOS, in order to achieve faster operation and lower switching energy. Examples include IMOS and FBFET that are operated in a non-equilibrium condition to rapidly generate mobile carriers. More recently, Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstance, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization–electrical field (P–E) curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. In this paper, a new threshold voltage model is developed to capture the feedback of negative capacitance and IV characteristics of Fe-FET. It is further revealed that the impact of random dopant fluctuation (RDF) on leakage variability can be significantly suppressed in Fe-FET, by tuning the thickness of the ferroelectric layer.

Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops

In this work, we have analyzed the effects of variability, due to random dopant fluctuation (RDF), on the timing characteristics of flip-flops for the future technology generations of 25, 18, and 13 nm, based on extensive Monte Carlo simulations. The results show that RDF has a significant impact on all of the timing parameters and that these parameters do not follow a normal distribution; in particular, they are skewed and exhibit a large tail. Moreover, the dispersion and skewness of the timing parameters increase with technology scaling. The study of the exact shape of these distributions, especially in the tail section, is of fundamental importance in the design and modeling of high-performance, reliable, and economically feasible circuits. In this paper, the distribution tails are estimated based on simulation data, with the aid of statistical nonparametric probability density functions, and it has been found that timing distributions can better be represented by certain nonparametric distributions, in particular Pearson and Johnson systems. The use of these representations during the statistical static timing analysis will provide more accurate results as compared with the normal approximation of distributions and will eventually reduce the probability of yield loss.

Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs

The effects of random dopant fluctuations (RDFs) on the performance of Germanium-source tunnel field-effect transistors (TFETs) is studied using 3-D device simulation. The RDF in the source region is found to have the most impact on threshold voltage variation (σ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) if the source is moderately doped (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) such that vertical tunneling within the source is dominant. If the source is heavily doped (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">20</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) such that lateral tunneling from the source to the channel is dominant, the impact of RDF in the channel region is also significant. RDF-induced threshold voltage variation (σ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) for an optimally designed Ge-source TFET is relatively modest (σ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> <; 20 mV at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Lg</i> = 30 nm), compared with a MOSFET of similar gate length. Supply voltage scaling is not beneficial for reducing TFET σ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> .

Impact of RDF and RTS on the performance of SRAM cells

This paper investigates electrical effects due to reliability phenomena associated with the downscaling of transistors in advanced technologies, particularly Random Telegraph Signal (RTS) and Random Dopant Fluctuations (RDF). RDF and RTS are becoming important issues in sub-60 nm technologies, mainly in memories, where transistor sizes are smaller. This paper presents a comprehensive evaluation of the impact of the joint effect of RTS and RDF on 6T-SRAM cells. Based on 3-D atomistic simulation of the device structure, doping profile, and trap location, the random threshold voltage variation caused by the joint effect of RDF and RTS is evaluated. The derived threshold voltage variation is then used to statistically evaluate the performance variation at the circuit level. Finally, the impact of assuming a normal distribution for the threshold voltage variation caused by RDF and RTS is studied. The results obtained running Monte Carlo simulations raffling the value of the variation of the threshold voltage from a database obtained by 3-D atomistic simulation are compared to the results obtained running Monte Carlo simulations considering the variation of the threshold voltage as a Normal distribution. The results show that for a 6T-SRAM designed with 45 nm technology the read noise margin distributions are very similar between the two cases, making the Normal distribution a good approximation for the V th variations. Nevertheless, the performance variation induced at the circuit level does not necessarily follow a normal distribution.

Performance Analysis of On-Chip Communication Structures under Device Variability

On-chip communication is becoming an important bottleneck in the design and operation of high performance systems where it has to face additional challenges due to device variability. Communication structures such as tapered buffer drivers, interconnects, repeaters, and data storage elements are vulnerable to variability, which can limit the performance of the on-chip communication networks. In this regard, it becomes important to have a complete understanding of the impact that variability will have on the performance of these circuit elements in order to design high yield and reliable systems. In this paper, the authors have characterized the performance of the communication structures under the impact of random dopant fluctuation (RDF) for the future technology generations of 25, 18, and 13 nm. For accurate characterization of their performance, a Monte Carlo simulation method has been used along with predictive device models for the given technologies. Analytical models have been developed for the link failure probability of a repeater inserted interconnect which uses characterization data of all communication structures to give an accurate prediction of the link failure probability. The model has also been extended to calculate the link failure probability of a wider communication link.

Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance

Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Among the sources of variability, line-edge-roughness (LER) and random dopant (RD) fluctuations are significant in current technology nodes. In this paper, the impact of the LER and RD on the matching performance of FinFETs is investigated for the LSTP-32 nm node, where these devices represent an attractive alternative to the planar CMOS transistors. Line-edge-roughness contributions from the fin, top-, and side wall-gates of n- and p-channel FinFETs are compared by means of 2-D and 3-D technology computer-aided design (TCAD) simulations, performed with a quantum-corrected hydrodynamic model on large statistical ensembles. Correlations between geometrical roughness and resulting electrical parameters are analyzed to provide further insight into the impact of the LER. A noise analysis approach is adopted to evaluate the impact of RD fluctuations throughout the impurity concentration ranges of interest, providing a direct comparison with the line-edge-roughness contributions. The impact of the extension doping profile specifications on the LER- and RD-induced mismatch is investigated, highlighting the potential drawbacks of junction engineering.