Impact Of Negative Bias Temperature Instability Research Articles

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Impact of Aging Degradation on Heavy-Ion SEU Response of 28-nm UTBB FD-SOI Technology

Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear applications up to space applications. The long-term reliability of these applications is essential for safe operation. However, the radiation effects for ICs are commonly investigated using fresh circuits, leaving the coupled effect of radiation and aging degradation unknown. This article investigates the impact of negative bias temperature instability (NBTI) aging degradation mechanism on the heavy-ion single event upset (SEU) radiation susceptibility of 28-nm ultra-thin body and buried oxide (UTBB) fully depleted silicon on insulator (FD-SOI) technology using a custom-designed test vehicle. NBTI aging degradation mechanism has been experimentally proven to increase the SEU sensitivity up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> for 28-nm UTBB FD-SOI flip-flops. A comprehensive framework is presented to analyze the underlying mechanisms for the impact of NBTI, which includes NBTI aging mechanism modeling, SEU SPICE simulation, TCAD irradiation simulation, and Monte-Carlo simulation of radiation effects. The framework offered a quantitative prediction of the effect of NBTI degradation mechanism on the heavy-ion SEU radiation sensitivity.

An Investigation for the Negative-Bias Temperature Instability Aware CMOS Logic

Background: Scaling of the dimensions of semiconductor device plays a very important role in the advancement of Very Large-Scale Integration (VLSI) technology. There are many advantages of scaling in VLSI technology such as increment in the speed of the device and less area requirement of the device. Aggressive device scaling causes some limitations in the form of short channel effects which produce large leakage current. Large leakage current harms the characteristics of the device and affects the reliability of the device. Objective: The most important and popular reliability issue in Deep Sub Micron (DSM) regime is Negative- Bias Temperature Instability (NBTI). NBTI effect increases the threshold voltage of p-channel Metal Oxide Semiconductor (PMOS) device over the time and affects the different characteristics of the device. As a result, circuit delay exceeds the design specification and there may be timing violations or logic failure. Different performance parameters are observed under NBTI effect for different logic gates. Methods: This paper presents an impact of NBTI at 22nm Berkeley short-channel IGFET model4 (BSIM4) Predictive Technology Model (PTM) for Complementary Metal Oxide Semiconductor (CMOS) logic gates. Reliability simulations are utilized to evaluate the amount of gradual damage in PMOS device due to NBTI effect. Results : The impact of NBTI degradation is checked for various CMOS logic gates using Mentor Graphics’s Eldo circuit simulator. Output voltage and drain current are reducing over the time under NBTI effect. Conclusion: NBTI degradation increases the threshold voltage of PMOS device over time and affects the different characteristics of the device.

Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and Mitigation

The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship's integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation.

Modeling of HCD Kinetics for Full ${V}_{{G}}$ /${V}_{{D}}$ Span in the Presence of NBTI, Electron Trapping, and Self Heating in RMG SiGe p-FinFETs

A SPICE compatible compact modeling framework is proposed for the time kinetics of threshold voltage shift ( $\Delta {V}_{T}$ ) in FinFETs subjected to hot carrier degradation (HCD) stress. The model is valid for the entire drain ( ${V}_{D}$ ) and gate ( ${V}_{G}$ ) voltage space and calculates the generation of interface traps for pure HCD ( $\Delta {V}_{\text {IT-HC}}$ ) and for negative bias temperature instability (NBTI) ( $\Delta {V}_{\text {IT-BT}}$ ), hole trapping ( $\Delta {V}_{\text {HT}}$ ), and electron trapping ( $\Delta {V}_{\text {ET}}$ ) as necessary, and considers the self-heating effect (SHE). The model is validated by using ultrafast (10- $\mu \text{s}$ delay) measured data from replacement metal gate (RMG) silicon germanium (SiGe) p-FinFETs having a different fin length (FL) and different nitrogen (N%) in the gate insulator stack. A calibrated TCAD framework is used to verify the impact of pure NBTI for varying ${V}_{G}$ and ${V}_{D}$ stress in the presence of SHE but no HCD.

Analysis of NBTI Degradation in nMOS-Capacitors and nMOSFETs

This paper presents a new attempt to further understand negative bias temperature instability (NBTI) stress in semiconductor devices. NBTI impact has been experimentally investigated on both p-substrate MOS (nMOS-capacitor) and nMOS transistors under accumulation condition, and new findings have been revealed. Indeed, nMOS-capacitor’s flat band shift ( $\boldsymbol {\Delta }\text{V}_{\mathbf {FB}}$ ) under NBTI stress has disclosed that time exponent ( ${n}$ ) and activation energy ( ${\mathbf{E}}_{\mathbf{a}}$ ) do vary with applied voltage stress pointing out to the contribution of two components, interface ( $\text{N}_{\mathbf {IT}}$ ) and oxide ( $\text{N}_{\mathbf {OT}}$ ) traps. Besides, the threshold electric field delimiting NBTI and stress induced leakage current can be well established. These findings have been confirmed by the appearance of a turn-around effect in nMOS transistors under NBTI stress. Moreover, charge pumping characterization has unveiled that NBTI degradation in nMOS transistor goes through two stages. First, only $\text{N}_{\mathbf {IT}}$ is created, then simultaneous generation of $\text{N}_{\mathbf {IT}}$ and $\text{N}_{\mathbf {OT}}$ takes part.

Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Negative Bias Temperature Instability (NBTI) is a key reliability and consistency issue for ultra-scaled Silicon IC technology with substantial consequences on both analog and digital circuit design For nano devices, NBTI apparently increases the threshold voltage exponentially on transient platform consequently, decreases the drain current and transconductance in the similar manner. The threshold voltage recovery function manifests the logarithmic transient reliance. The issue is of critical perturb, especially in p-channel nanoscale MOS devices, as these devices generally operate with negative gate-to-source voltage Use of high-K dielectric stack enhances the NBTI impact on these nano devices The manuscript investigates and models the NBTI characteristics for bulk driven nanoscale p-MOS device with ultrathin high-K gate dielectric stack. The gate terminal is transiently negatively biased and further relaxed with positive bias conditions for ample time for the recovery of the initial characteristics. Threshold voltage shift at various gate bias conditions and diverse temperatures demonstrate that NBTI is highly subjugated by the defect generation and hole trapping bustle in gate dielectric pre-existing traps NBTI recovery is accelerated by increasing the temperature. Threshold voltage shift in recovery phase showed a swift initial transient, ensued by an acutely sluggish, passive non-exponential transient. A compact NBTI model for nano MOSFET is proffered capturing the dependency of stress phase gate bias, recovery gate voltage and operating temperature Importantly, only the restricted bunch of fitting parameters are required for anticipation. The proposed NBTI model is valid for FD/SOI/FinFET technology also and can be easily implemented on TCAD circuit simulators.

Analysing NBTI Impact on SRAMs with Resistive Defects

Density’s increase in Static Random Access Memory (SRAM) has become an important concern for testing, since new types of defects, that may occur during the manufacturing process, are introduced. On the one hand, new manufacturing defects may lead to dynamic faults, which are considered one of the most important causes of test escape in deep-submicron technologies. On the other hand, the SRAM’s robustness is considered crucial, since it may affect the entire SoC. One of the most important phenomena to degrade SRAM reliability is Negative-Bias Temperature Instability (NBTI) causing the memory cells’ aging. In this context, the paper proposes to analyse the impact of NBTI on SRAM cells with resistive defects that eventually escape manufacturing test and, with aging, may generate faults over time. Finally, SPICE simulations adopting a commercial 65 nm CMOS technology library have been performed in order to estimate NBTI’s precise impact over time.

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

For sub-20-nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, negative bias temperature instability (NBTI) is an important reliability issue and requires an accurate model to predict device and circuit performance. In this paper, we report a well-calibrated predictive and scalable compact Verilog-A-based compact model, integrated with an NBTI model for NW CMOS circuit simulation and design. The stress and recovery NBTI model for an Si NW field-effect transistor is obtained from experimental NW pMOSFETs using a range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar metal-oxide semiconductor field-effect transistors. This is attributed to its cylindrical gate structure, resulting in enhanced 2-D hydrogen diffusion and stress-induced Si/SiO2 traps. This emphasizes the need to evaluate NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: an inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, the interface states generation, inverter delay, and RO frequency degrade rapidly and saturate over the long-term 10-year lifetime. Finally, the design of the SRAM cell employing the multiwire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using the appropriate design configuration. This paper underscores the need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at the device and circuit level.

Impact of NBTI induced variations on delay locked loop multi-phase clock generator

Negative bias temperature instability (NBTI) is a serious reliability concern for both analog and digital CMOS VLSI circuits. The shift in threshold voltage and reduction in drain current due to NBTI in p-channel MOSFETs are time, bias and temperature dependent. The degradation of the PMOS at any critical nodes in the circuit leads to the failure of the circuit immediately or in few months/year. The Delay-Locked-Loop (DLL) which is used as multi-phase clock generator for microprocessors, frequency synthesizers, time-to-digital converter (TDC) etc. reduces the phase error between output and reference clock until it is locked. The delay variations due to process, voltage and temperature fluctuations are governed by its feedback system. At start-up, the phase shift of the output clock should lie between 0.5 and 1.5 times the time period of the reference clock to achieve regular locking. The deviations from the above criteria due to NBTI degradation directly affect the control system and lead to erroneous locking. The NBTI-induced time-dependent variation in PMOS of the delay stage in voltage-controlled delay line (VCDL) of DLL affects the delay in each stage of VCDL and propagates as phase error to the output clock. This paper analyzes the impact of NBTI-induced time-dependent variations in Delay-Locked-Loop (DLL) based clock generators for the first time. The DLL is designed with 180nm technologies with working frequency range from 75MHz to 220MHz. The time dependent variations in VCDL, the most sensitive blocks of DLL, are analyzed. It is observed that these time-dependent variations increase the phase error and the working of DLL is severely affected at the rearmost end of frequency range. The output clock gets deviated and observed to be locked late after π/2 or π radians from the nominal lock. It is essential to prevent DLL locking to an incorrect delay or false lock and to bring the output clock back to the correct position. An adaptive body bias circuit is proposed in this paper to reduce the impact of NBTI degradation and thereby to prevent erroneous locking in DLL.

Mitigating the Impact of NBTI and PBTI Degradation

Modern CMOS devices encounter a major problem that alters the threshold voltages of the NMOS and PMOS. Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) are common ageing phenomena observed in PMOS and NMOS devices, respectively. Due to operating temperature and stress time, NBTI and PBTI create a decrease in drain-to-source current and an increase in propagation delay. Threshold voltage is an important parameter due to exponential dependence on delay and leakage power. Threshold voltage variations produce adverse effects on operation frequency. These phenomena accrue in pull-up/pull-down transistors in stack and vastly degrade CMOS performance. This paper discusses the various factors responsible for NBTI and PBTI and the challenges associated with modeling these effects due to the recovery mechanism exhibited by the transistors when the stress is removed. Therefore, we propose an algorithm to reduce the effects of NBTI and PBTI that will reduce the stress time for each transistor through the relative repositioning of the transistors based on the signal probability.

Development of a Technique for Characterizing Bias Temperature Instability-Induced Device-to-Device Variation at SRAM-Relevant Conditions

SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-(I) -(V) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias.

Energy Distribution of Positive Charges in &lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;${\rm Al}_{2}{\rm O}_{3}{\rm GeO}_{2}/{\rm Ge}$&lt;/tex&gt;&lt;/formula&gt; pMOSFETs

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3-GeO2-Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3/GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3/GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise.

Understanding Process Impact of Hole Traps and NBTI in HKMG p-MOSFETs Using Measurements and Atomistic Simulations

The impact of the gate insulator process on interlayer (IL) hole traps in IL/high-K dual-layer p-MOSFET gate-stack is studied by physical and electrical measurements along with atomistic simulations. Processes that lead to higher concentrations of Hf and N in IL, measured by angle-resolved X-ray photoelectron spectroscopy, result in higher IL hole traps measured by flicker noise in prestress and verified by atomistic simulations. The influence of these process induced preexisting IL hole traps on parametric degradation of p-MOSFETs during Negative bias temperature instability (NBTI) stress is studied. The mechanism responsible for superior NBTI of thermal IL stack, having lower Hf and N content in the IL as compared with Chem-Ox IL stack, is explained.

Skew Management of NBTI Impacted Gated Clock Trees

Negative bias temperature instability (NBTI) has emerged as the dominant failure mechanism for PMOS devices in nanometer integrated circuit (IC) designs, thus limiting their lifetime. There are several existing research works that mitigate impact of NBTI on gate delay and reliability. However, its impact on one of the most important components of modern IC design-the clock tree-has not been researched enough. Clock gating impacts the extent of NBTI-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> degradation of clock buffers leading to nonuniform NBTI degradation and, thus, increased clock skew. In this paper, we propose a practical design-time technique of modifying the clock gating implementation by selecting NAND or NOR gate as output stage of integrated clock gating cells with the objective of minimizing NBTI-induced clock skew. This selection intelligently modulates the signal probability and delay equations of clock signal paths with no extra hardware penalty. We formulate the skew minimization problem as an integer linear program which determines the optimal NAND or NOR assignment of clock gating buffer. Experimental results demonstrate the effectiveness of our method as the NBTI-induced clock skew is reduced by more than 74% compared to the traditional method. The impact of voltage and temperature variation on the proposed technique was analyzed and we observed reduced but still significant reduction in clock skew under variation as compared to the traditional clock gating technique.

Impact Analysis of NBTI/PBTI on SRAM VMINand Design Techniques for Improved SRAM VMIN

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM VMIN, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM VMIN. Two different types of SRAM VMIN (SNM-limited VMIN and time-limited VMIN) are explained. Simulation results show that SNM-limited VMIN is more sensitive to NBTI while time-limited VMIN is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the VMIN degradation induced by NBTI/PBTI.

A Comparative Study of Different Physics-Based NBTI Models

Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.

Statistical forecasting algorithm on circuit level gain transformation due to negative bias temperature instability for the microwave frequency spectrum

Negative Bias Temperature Instability (NBTI) is a critical reliability issue for CMOS technology, as this directly impacts the CMOS circuit performance parameters causing system failure. Moreover, NBTI behavior for radio frequency (RF) signals needs more understanding. On the device level, there has been much research on the relation between NBTI and RF. Many of those works contradict each other on the question of RF dependency with NBTI. Hence, the behavior of NBTI must be analyzed at the circuit level using a prediction technique. In this article, we analyzed the circuit level impact of NBTI for microwave frequency and developed a gain transformation technique for RF circuits in the microwave frequency range. To do this, we employed a 65 nm conventional ring oscillator as an RF block and carried out an aging simulation on it. A compatibility analysis was performed on low and high bandwidth microwave signals. The implemented statistical technique can determine the actual operable frequency range, so that the RF circuit can perform with minimal NBTI effect.

Reliability Implications of NBTI in Digital Integrated Circuits

Bias temperature instability (BTI) in MOSFETs in one of the major reliability challenges in nano-scale technology. This paper evaluates the severity of Negative BTI (NBTI) degradation in two major circuit applications: random logic and memory array. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. Simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memories results in severe READ stability degradation, especially when combined with random process variation. Moreover, in scaled technology nodes, finite number of Si-H bonds in the channel can induce a statistical random variation in the degradation process. Simulations using 32nm/22nm Predictive Technology Model (PTM) shows that statistical random variation of NBTI, on top of random dopant fluctuation (RDF) results in significant random Vt variation in PMOS transistors, resulting in considerable degradation in static noise margin (SNM) of memory cells.

Technology Scaling Effect on the Relative Impact of NBTI and Process Variation on the Reliability of Digital Circuits

The impact of negative bias temperature instability (NBTI) on circuit reliability is typically assessed without accounting for the variability associated with the manufacturing process. With technology progression, manufacturing process variability scales more aggressively than transistor NBTI lifetime. Hence, a clear link between transistor and circuit reliability that takes variability into account is imperative to analyze circuit reliability. We propose a figure of merit termed fall-out to describe the proportion of circuits whose frequencies would exceed the initial manufacturing distribution. We use fall-out to assess NBTI and process variability in tandem, and we show that the fall-out of circuit frequency (or timing delay) peaks and diminishes as technology scales. We propose that the fall-out of a ring oscillator can be used as a worst-case indicator of circuit reliability in any given technology.