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Abstract
The impact of the gate insulator process on interlayer (IL) hole traps in IL/high-K dual-layer p-MOSFET gate-stack is studied by physical and electrical measurements along with atomistic simulations. Processes that lead to higher concentrations of Hf and N in IL, measured by angle-resolved X-ray photoelectron spectroscopy, result in higher IL hole traps measured by flicker noise in prestress and verified by atomistic simulations. The influence of these process induced preexisting IL hole traps on parametric degradation of p-MOSFETs during Negative bias temperature instability (NBTI) stress is studied. The mechanism responsible for superior NBTI of thermal IL stack, having lower Hf and N content in the IL as compared with Chem-Ox IL stack, is explained.
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