Impact Of Line Edge Roughness Research Articles

Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance

Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Among the sources of variability, line-edge-roughness (LER) and random dopant (RD) fluctuations are significant in current technology nodes. In this paper, the impact of the LER and RD on the matching performance of FinFETs is investigated for the LSTP-32 nm node, where these devices represent an attractive alternative to the planar CMOS transistors. Line-edge-roughness contributions from the fin, top-, and side wall-gates of n- and p-channel FinFETs are compared by means of 2-D and 3-D technology computer-aided design (TCAD) simulations, performed with a quantum-corrected hydrodynamic model on large statistical ensembles. Correlations between geometrical roughness and resulting electrical parameters are analyzed to provide further insight into the impact of the LER. A noise analysis approach is adopted to evaluate the impact of RD fluctuations throughout the impurity concentration ranges of interest, providing a direct comparison with the line-edge-roughness contributions. The impact of the extension doping profile specifications on the LER- and RD-induced mismatch is investigated, highlighting the potential drawbacks of junction engineering.

Impact of Line-Edge Roughness on FinFET Matching Performance

As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact of LER on the matching performance of FinFETs is investigated through statistical device simulations, comparing the relative importance of fin- and gate-LER. Fin-LER is shown to significantly degrade FinFET matching performance under DC and transient operations. Combining our device simulation results with experimental data, it is shown that fin-LER will dominate the intra-bit-cell stochastic mismatch in FinFET static random access memories at the LSTP-32-nm node. The electrical performance of spacer-defined fin (SDF) and resist-defined fin (RDF) patterning technologies has been compared. It is shown that, with respect to RDF patterning, the spacer-defined process has the potential to improve FinFET matching performance by 90%.

Impact of line-edge roughness on resistance and capacitance of scaled interconnects

The impact of line-edge roughness (LER) on resistance R and capacitance C of on-chip interconnects is for the first time evaluated by a simulation methodology based on a realistic modeling of LER. The model can be calibrated with measured LER parameters. A geometrical approximations of LER is generated and superimposed to an interconnect architecture model with no roughness; resistance and capacitance are extracted from the model by a 3D static solver to estimate the impact of LER on them. By applying this methodology to the interconnect scaling scenario of the 2005 ITRS Roadmap, a small but increasing detrimental effect of LER on both R and C is predicted.

Impact of line edge roughness on copper interconnects

The dimensions of transistor gates are scaling to small dimensions and the relative variation of the edge, referred to as line edge roughness (LER), is addressed as one of the critical issues for front-end technology. These local variations deteriorate the device performance [Croon et al., Tech. Dig. - Int. Electron Devices Meet. 2002, 307; Croon et al., Proceedings of the ESSDERC, 2003 (unpublished), p. 22]. However, also for backend, interconnects wires are scaling down and the relative contribution of the LER is increasing. The impact of LER for interconnects has rarely been studied yet. In this article we address the electrical performance of the resulting copper interconnects with additional LER generated with e-beam lithography. The added LER will have spatial frequencies and amplitudes that are similar to the current resists used.

Spectral analysis of line-edge roughness in polyphenol EB-resists and its impact on transistor performance

Resists using polyphenol resin are introduced to reduce line-edge roughness (LER), and the spatial frequency characteristics of LER are evaluated. It is found that the long-period components of LER are suppressed in our low molecular-weight polyphenol resists. Device simulation using the measured LER shows that our polyphenol-based resist can drastically reduce the number of low-threshold-voltage (Vth) transistors compared with a conventional resist due to reduced long-period LER. Because LER impact is more serious as the transistor width shrinks, our results suggest that the use of the polyphenol-type resist will be more effective in improving device performance in future lithography process. In addition, it is shown that spectral analysis is a powerful tool for LER evaluation, especially from the viewpoint of device performance estimation.

Experimental Investigation of the Impact of LWR on Sub-100-nm Device Performance

Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.

Impact of line edge roughness on the resistivity of nanometer-scale interconnects

The impact of line edge roughness on the resistivity of copper interconnects in the sub-100 nm range has been calculated. An analytical model has been derived in order to describe the resistivity change. It has been found, that the resistivity is significantly increased compared to interconnect structures with smooth sidewalls for linewidths smaller than 50 nm and peak-to-peak variations of the widths exceeding 30 nm. As root causes of the increase geometrical effects combined with the size-dependent resistivity increase of nanometer-scale interconnects have been identified. Therefore, similar results are expected to apply for other metallization schemes, for example subtractively patterned aluminum.

EUV Lithography: Patterning to the End of the Road

AbstractExtreme Ultraviolet (EUV) lithography is gaining momentum as the patterning technology of choice for the semiconductor nodes with less than 70-nm half-pitch. As such, it must be ready for manufacturing in the 2006-2007 time frame, and it must be extendable to the lower limits of CMOS technology. Successful patterning of 40-nm dense lines in viable EUV photoresists indicates that today's resist materials may have the necessary resolution, but better optics are needed to verify this more rigorously. Although little is understood about the impact of line-edge roughness (LER) on device performance, it is generally assumed that EUV LER must be less than 3 nm 3σ. EUV lines have been printed with LER as low as 4 nm 3σ, but they were printed with unacceptable photospeed. Deliberate attempts to increase the photospeed while maintaining low LER have produced a resist with sizing dose of 1.7 mJ/cm2 and LER of 6.6 nm 3σ. Photospeed is important because EUV photons are difficult to create, and the photoresist must use them efficiently for economically acceptable throughput. Throughput models indicate that patterning doses may need to be 1-2 mJ/cm2, and only 30-40% of these photons will be absorbed, so the resists must be able to accommodate statistical dose fluctuations that are an appreciable fraction of the mean dose. Highly sensitive resists such as these have been produced with good LER. Since all resist materials absorb EUV radiation strongly, the photoresist layer will have to be less than 150 nm thick. Resists this thin pose problems for device manufacturing, largely because they will not have acceptable etch resistance, and this etch resistance will have to be recovered in some other way. Efforts have begun to integrate hard masks with thin resists in real device fabrication. Defect data indicate that defect densities do not increase in resist films less than 100 nm thick, and transistors, via chains, and microprocessors have all been fabricated with these thin-resist/hard-mask integrations.