Impact Ionization MOSFET Research Articles

L-Shaped Double Gate Bipolar Impact Ionization MOSFET Based Energy Efficient Leaky Integrate and Fire Neuron for Spiking Neural Network

L-Shaped Double Gate Bipolar Impact Ionization MOSFET Based Energy Efficient Leaky Integrate and Fire Neuron for Spiking Neural Network

Analytical Modelling of Dopingless (DL) Impact Ionization MOSFET (IMOS)

Analytical Modelling of Dopingless (DL) Impact Ionization MOSFET (IMOS)

A low power L-shaped gate bipolar impact ionization MOSFET based capacitorless one transistor dynamic random access memory cell

In this paper, a capacitorless, low power and CMOS compatible L-shaped gate bipolar impact ionization metal-oxide semiconductor (L-BIMOS) one transistor dynamic random access memory (1T DRAM) cell is proposed. The proposed 1T DRAM offers high retention time (RT = ∼1.4 s), sense margin (SM = ∼45 μA μm−1) and read current ratio (∼5 orders of magnitude). The RT and SM are 1.86×, and 300× , respectively higher than the previously reported silicon germanium (SiGe) based BIMOS 1T DRAM. Therefore, the proposed 1T DRAM cell stands out to be power efficient, and provides better integration density that makes it suitable for various emerging computing applications.

In-Depth Design and Simulation Analysis of Vertical Strained Impact Ionization MOSFET (VESIMOS)

The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET (VESIMOS) has been successfully design and analyzed in this paper. VESIMOS device integrates vertical structure concept of Impact Ionization MOSFET (IMOS) and strained technology. The transfer characteristics of VESIMOS revealed an inverse proportionality between supply voltage, VD and sub-threshold, S due to lower breakdown strength of Germanium (Ge) content. The S=10mV/dec was successfully obtained at threshold voltage, VT=0.9V, with VD=1.75V. This VT is found to be 40% lower than VT for conventional Si-vertical IMOS. The output characteristics goes into saturation for VD more than 2.5V, attributed to the presence of Ge that has high and symmetric impact ionization rates. Electron mobility was improved by 40% compared to conventional Si-vertical IMOS. The increase in strain layer thickness, TSiGe, resulted in an increase of VT and lowered the mobility due to the strain relaxation in the SiGe layer. For high source-drain doping concentration, S/D=2x1018/cm3, the VT dropped to 0.88V, with VD of 1.75V due to high electric field effect in the channel, which is found to be contrary to the doping effects of conventional MOSFET. In every aspect, VESIMOS is projected to be premier candidate for future nanoelectronics device as to prolonged the scaling of conventional MOSFET into nano-regime.

Breakdown Voltage Reduction Analysis with Adopting Dual Channel Vertical Strained SiGe Impact Ionization MOSFET (VESIMOS)

The Single and Dual Strained SiGe layer for Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET (VESIMOS) have been successfully analyzed in this paper. It is found that the drain current for single (SC) and dual channel (DC) VESIMOS were increased sharply initially due to the presence of Germanium. Germanium has high impact ionization rates to ensure that the transition from OFF state to ON state is abrupt. However, breakdown voltage of the SC device was decreased from B.=2.9V to 2.5V by increasing the composition of Ge from 10% to 30%. The same characteristics were found for DC VESIMOS where Bv= 2V had decreased to 1.6V by varying the Ge composition. In short, the breakdown voltage which affected by the appearance of the second SiGe channel and Ge composition was justified. Apart from that, with the presence of the second SiGe channel, the switching speed and ION/IOFF of the device were improved. It was found that the sub-threshold slope of SC and DC VESIMOS were inversely proportional to the breakdown voltage.

Simulation-Based Ultralow Energy and High-Speed LIF Neuron Using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks

The silicon bipolar impact ionization MOSFET offers potential for the realization of leaky integrated fire (LIF) silicon neuron due to the presence of parasitic bipolar junction transistor (BJT) in the floating body. In this article, we have proposed an L-shaped gate bipolar impact ionization MOS (L-BIMOS) with reduced breakdown voltage ( ${V}_{B} = {1.68}$ V) and demonstrated the functioning of LIF neuron based on the positive feedback mechanism of parasitic BJT. Using the 2-D TCAD simulations, we manifest that the proposed L-BIMOS exhibits a low threshold voltage (0.2 V) for firing a spike, and the minimum energy required to fire a single spike for L-BIMOS is calculated to be 0.18 pJ, which makes the proposed device 194 times more energy efficient than the PD-SOI MOSFET silicon neuron and ${5}\times {10}^{{3}}$ times more energy efficient than the analog/digital circuit-based conventional neurons. Furthermore, the proposed L-BIMOS silicon neuron exhibits spiking frequency in the gigahertz range when the drain is biased at ${V}_{\text {DG}} = {2.0}$ V.

An Impact Ionization MOSFET With Reduced Breakdown Voltage Based on Back-Gate Misalignment

In this paper, we propose a misaligned double-gate p-i-n impact ionization MOS (MIMOS) with a deliberate misalignment between the top and bottom gates. The presence of a misaligned bottom gate leads to band-to-band-tunneling of electrons at the source-intrinsic region interface and increases the number of carriers for impact ionization. The electric field redistribution provides a longer transport path for the carriers. Therefore, carriers gain higher kinetic energy, and the impact ionization rate is enhanced in the MIMOS. This results in a significantly lower avalanche breakdown voltage compared to conventional single-gate IMOS structure. Using calibrated 2-D simulations, we demonstrate that MIMOS exhibits a steep subthreshold slope (~6 mV/dec) at a significantly low-supply voltage of ( ${V}_{\text {DS}}= {0.59}$ V), which is ~48% lower than that of the corresponding single-gate IMOS ( ${V}_{\text {DS}}= {1.15}$ V).

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG (dual material gate) DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better ION, ION/IOFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized performance is achieved including ION/IOFF ratio of 2.87 × 109 A/μm with ION as 11.87 × 10−4 A/μm and transconductance of 1.06 × 10−3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.

Enhanced Reliability of Vertical Strained Impact Ionization MOSFET Incorporating Dielectric Pocket for Ultra-Sensitive Biosensor Applications

Fast switching with an enhanced reliability device structure of Vertical Strained Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP) has been successfully design, simulated and analyzed in this paper. Ultra-low power with low subthreshold swing (S) and high breakdown voltage are imperative for ultra-sensitive biosensors. Impact ionization MOSFET (IMOS) is predicted to be capable of S as low as 20 mV/dec, which is much lower than Conventional MOSFET (CMOS). There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. S value for DP place at source side is higher (S 24.4 mV/decade) as compared at the drain side (S 18.9 mV/decade) intrinsic region. The vicinity of DP near the drain region reduces charge sharing effects associated with the source and thus improves impact ionization rate. The introduction of a Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the reliability of the device by attaining higher breakdown voltage. Consequently, with the reduced of alloy scattering, the electron mobility has been improved by 22%. In many aspects, it is revealed that the incorporation of DP enhanced the reliability of VESIMOS for future development of nanoelectronic devices.

Vertical Strained Impact Ionization MOSFET (VESIMOS) Technology Approach for Based Biosensor Applications Using Its Behavioral Model

This paper gives an overview about uniqueness characteristics of Vertical Strained Impact Ionization MOSFET (VESIMOS) technology act as bio-sensing devices. There are three proposed devices used VESIMOS technology which are Single Channel VESIMOS (SC-VESIMOS), Dual Channel (DC-VESIMOS), VESIMOS Incorporating Dielectric Pocket (VESIMOS-DP) are probably can become feasible candidates as biosensor devices. The selected devices from three structures was further analyzed for its behavioral model. The extracted parameter from the device simulations was used to design the circuitry model to represent the characteristic and behavior of the selected devices in circuit implementation. The best characteristic of the device shown by DC-VESIMOS and selected for further analysis. The behavioral model or equivalent circuit model of DC-VESIMOS used PSPICE circuit simulator. Main prerequisite of biosensor device are high sensitivity, faster response, and high reliability which represented by the VESIMOS structures. Low subthreshold swings present the sensitivity of the devices shown by DC-VESIMOS are 11.48 mV/dec and 10.53 mV/dec from TCAD and PSPICE results respectively.

A Novel Cascade-Free 5-V ESD Clamp Using I-MOS: Proposal and Analysis

In this paper, we present a new ESD device using the p-channel impact ionization MOSFET (I-MOS) with its gate and source connected to the ground, and its drain connected to the input/output (I/O) pad, called as the gate grounded I-MOS (GGIMOS). The proposed GGIMOS uses the conventional thick oxide (used for 2.5-V I/O devices) for 5-V failsafe/fault-tolerant I/O applications. For positive electrostatic discharge (ESD) stress, the turn-on mechanism is through controlled avalanche multiplication. During negative stress, the GGIMOS acts as a forward-biased gated diode. The gate oxide reliability concern of the p-channel I-MOS is alleviated by implementing the device in the p-substrate instead of n-well. The physics and operation of the GGIMOS is explained using electrothermal technology computer-aided design simulations and its performance is benchmarked using the simulated transmission line pulsing (TLP), very fast TLP, and human body model results. The proposed device eliminates the need for: 1) a cascaded nMOS architecture for high-voltage capability; and 2) a return diode for negative ESD stress conditions resulting in an area-efficient ESD clamp design. This makes the GGIMOS a potential device for ESD clamping applications in the state-of-the-art CMOS technologies.

Analytical modeling of Schottky tunneling source impact ionization MOSFET with reduced breakdown voltage

In this paper, we have investigated a novel Schottky tunneling source impact ionization MOSFET (STS-IMOS) to lower the breakdown voltage of conventional impact ionization MOS (IMOS) and developed an analytical model for the same. In STS-IMOS there is an accumulative effect of both impact ionization and source induced barrier tunneling. The silicide source offers very low parasitic resistance, the outcome of which is an increment in voltage drop across the intrinsic region for the same applied bias. This reduces operating voltage and hence, it exhibits a significant reduction in both breakdown and threshold voltage. STS-IMOS shows high immunity against hot electron damage. As a result of this the device reliability increases magnificently. The analytical model for impact ionization current (Iii) is developed based on the integration of ionization integral (M). Similarly, to get Schottky tunneling current (ITun) expression, Wentzel–Kramers–Brillouin (WKB) approximation is employed. Analytical models for threshold voltage and subthreshold slope is optimized against Schottky barrier height (ϕB) variation. The expression for the drain current is computed as a function of gate-to-drain bias via integral expression. It is validated by comparing it with the technology computer-aided design (TCAD) simulation results as well. In essence, this analytical framework provides the physical background for better understanding of STS-IMOS and its performance estimation.

Novel charge plasma based dielectric modulated impact ionization MOSFET as a biosensor for label-free detection

In this paper a charge plasma based dielectric modulated impact ionization MOSFET (CP-DIMOSFET) has been proposed for the first time to ease the label free detection of biomolecules. The concept of CP-DIMOSFET is proposed and analyzed on basis of simulated data using SILVACO ATLAS. Low thermal budgeting and thin silicon layer without any dopant implantations make the proposed structure advantageous compared to the existing MOSFET based biosensors. The results show that the proposed device is capable to detect the presence of biomolecules. Simple fabrication schemes, miniaturization, high sensitivity, dominance of dielectric modulation make the proposed biosensor a promising one that could one day revolutionize the healthcare industry.

Effect of the Ge Mole Fraction on the Electrical Characteristics of Single and Dual Channel Vertical Strained SiGe Impact Ionization MOSFET (VESIMOS)

The effect of the Ge mole fraction in a Si1-xGex on single and dual channel Vertical Strained SiGe Impact Ionization MOSFET was successfully analyzed. It is found that the threshold voltage, breakdown voltage and sub-threshold slope of the devices was affected by the presence of the Germanium. A better performance in sub-threshold voltage of the devices was obtained for dual channel VESIMOS compared to single channel VESIMOS with a suitable amount of Germanium. Germanium has high and symmetric impact ionization rates to ensure the transition from OFF state to ON state is abrupt. With the appearance of the SiGe layer in the devices, has an advantage of the mobility enhancement of carriers in the devices operation. With the improvement of the Ge composition, it could transform VESIMOS into a new paradigm of devices which applicable to nanoelectronics with better electrical characteristics.

Statistical Retardation Delay of I-MOS and Its Measurement Using TDR

In this letter, we study the statistical retardation delay of the impact ionization MOSFET (I-MOS) that is observed during the turn-on transient. Since seed carriers are required to initiate an avalanche breakdown in the I-MOS, the turn-on delay of the I-MOS has an additional random component associated with the generation of seed carriers. The characteristics of this delay are statistically analyzed and measured for the first time with time-domain reflectometry. The results show a fundamental limitation of the I-MOS delay, which is directly associated with the leakage current.

The Impact Ionization MOSFET (IMOS) as low-voltage optical detector

Avalanche photodiodes are widely used in a variety of applications. However, they need a high supply voltage. We propose to use the Impact Ionization MOSFET (IMOS) as an optical detector because it could substitute the high drain voltage by an internal amplification mechanism. Therefore, a much lower supply voltage would be needed. We fabricated devices as the first proof of principle and showed that the proposed concept works. We identified the most important problem of the actual devices and will do further research in order to improve the performance and reach towards the performance of avalanche photodiodes.

Investigation of the performance of strained-SiGe vertical IMOS-transistors

A vertical impact ionization MOSFET (IMOS) with a thin layer of biaxially strained SiGe in the impact ionization (II) region near the drain and in the channel is thoroughly investigated by Full-Band Monte Carlo (FB-MC) and Hydrodynamic simulations. An anisotropic II model based on the constant matrix element approximation is integrated into the FB-MC to simulate II in relaxed-Si- and strained-SiGe-Vertical-IMOSs. The II generation currents obtained by FB-MC are, in turn, used to calibrate the II model of the Hydrodynamic simulator. The final results show that the reduction of the energy barrier caused by the strained SiGe layer in the channel improves the IMOS characteristic by lowering the threshold voltage. However, when the strained SiGe layer is placed in the region with the highest II near the drain, an improvement of the vertical IMOS by a higher II rate of the strained layer is not observed.

Epitaxy — A way to novel field effect devices

This paper presents an overview of the fabrication and the performance of two promising candidates for succession of the conventional MOSFET: the Tunneling FET (TFET) and the vertical Impact Ionization MOSFET (I-MOS). These devices offer possibilities to overcome physical limits occurring during the continuous shrinking process like the limitation of the subthreshold swing S to 60 mV/dec at room temperature or rising leakage currents due to tunneling. The performance of these novel devices strongly depends on the shape, level and sharpness of the doping profiles in the active regions. Therefore their fabrication using the vertical transistor concept and epitaxial growth to build the active layers is a very suitable way to achieve a very good device performance.

Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied Ω- and tri-gate structures to obtain abrupt switching (3–10mV/decade) combined with a hysteresis in the ID(VDS) and ID(VGS) characteristics. The PIMOS device shows an extraordinary temperature stability up to 125°C. The influence of various parameters on device performance as abrupt switch or memory cell is investigated. Reduction of the electrical channel length, i.e. of gate length and/or substrate doping, reduces the breakdown voltage and hence the DRAM operating voltage, but also increase the Ioff. Two architectures for a capacitor-less DRAM cell are demonstrated and evaluated. In addition, a PIMOS n-type hysteretic inverter is demonstrated, which may serve as a 1T SRAM cell.

Doping profile dependence of the vertical impact ionization MOSFET’s (I-MOS) performance

This paper presents experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical impact ionization MOSFET (I-MOS). The device is fabricated as a gated n +ip +in + structure, where the p + region is a (as grown) 3 nm thin highly doped delta layer. The final shape of the doping profiles strongly depends on the thermal budget during processing and influences the electrical characteristics. Especially the subthreshold slope S strongly depends on the shape of the doping profiles. Values of S as low as 1.06 mV/dec were measured using this device concept. We will explain the effects influencing the electrical behavior by measurements and simulations.