ILP-based Method Research Articles

Investigation of home appliances industry and devices obsolescence considering energy consumption

The objective of this study is to optimize a linear objective function that pertains to the obsolescence of home appliances in a household. The approach introduced is an ILP-based method that is both simple and adaptable. This optimization guarantees that the total energy consumption remains below a predetermined energy threshold, while also adhering to an inequality constraint. The proposed methodology was effectively tested using a household containing four home appliances: a washing machine, a dishwasher, a refrigerator, and an oven. The findings indicate that the refrigerator is the most hazardous and inexpensive home appliance. The current formulation aims to optimize the device's lifespan considering the customer's financial constraints and the expenses associated with repairing and replacing its parts. This study centers on the maintenance of printed circuit boards (PCBs) and considers the effects of degradation-related malfunctions, as assessed through testing. Moreover, we employ an additional ILP approach to assess the vulnerability of refrigerator’s PCB components by determining which ones should be replaced when a customer has limited financial resources.

FragQC: An efficient quantum error reduction technique using quantum circuit fragmentation

Quantum computers must meet extremely stringent qualitative and quantitative requirements on their qubits in order to solve real-life problems. Quantum circuit fragmentation techniques divide a large quantum circuit into a number of sub-circuits that can be executed on the smaller noisy quantum hardware available. However, the process of quantum circuit fragmentation involves finding an ideal cut that has exponential time complexity and also the classical post-processing required to reconstruct the output. In this paper, we represent a quantum circuit using a weighted graph and propose a novel classical graph partitioning algorithm for selecting an efficient fragmentation that reduces the entanglement between the sub-circuits along with balancing the estimated error in each sub-circuit. We also demonstrate a comparative study of different classical and quantum approaches to graph partitioning for finding such a cut. We present FragQC, a software tool that cuts a quantum circuit into sub-circuits when its error probability exceeds a certain threshold. With this proposed approach, we achieve an increase in fidelity of 13.38% compared to direct execution without cutting the circuit, and 7.88% over the state-of-the-art ILP-based method for the benchmark circuits.The code for FragQC is available at https://github.com/arnavdas88/FragQC.

Don’t-Care-Based Logic Optimization for Threshold Logic

In this paper, we present a don’t-care-based threshold logic gate (TLG) minimization method for threshold logic network (TLN) optimization. We first introduce a sufficient condition for the don’t cares of a TLG to exist in a TLN and propose a logic-implication-based method to identify the don’t cares. Then, we present two different methods for minimizing the TLG with the don’t cares. The first one is an integer linear programming (ILP)-based method. We model the minimization problem as an ILP problem, and propose an approach to compute the necessary constraints of the ILP formulation. The second one is a heuristic method adapted from a threshold function identification approach. In the experiments, we applied the proposed methods to two sets of TLNs generated by the up-to-date synthesis technique. The results show that, for the two sets of TLNs, the ILP-based method achieves an average of 12% and 23% area reduction without any overhead on the TLG count and logic depth. Furthermore, the heuristic method is more efficient than the ILP-based method with only a little quality loss.

Rumor Containment by Blocking Nodes in Social Networks

Rumor spreads fast in social networks and may seriously damage our society. In this article, we present a mathematical programming formulation based on integer linear programming (ILP) to minimize rumor spread by blocking a subset of nodes (called blockers) in complex social networks modeled as a linear threshold model. We also propose a modified approach which solves the top- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$</tex-math> </inline-formula> blockers problem with a reduced computational effort and formally proves that its performance is still optimal. Then, the presented method is evaluated for its effectiveness of containing rumor spread in four different networks and its performance is compared with a greedy-based and two centrality-based approaches. The experimental analysis shows that the ILP-based method outperforms the other three approaches and is applicable to large-scale networks.

Integer programming model and branch-and-cut algorithm for the stack inbound and pre-marshalling problem

The steel plate yard of shipbuilding separates the inbound and pre-processing operations, increasing the number of moves. This paper considers the mixed inbound and pre-processing operation and studies the stack inbound and pre-marshalling problem where storage and relocation moves can alternate. This problem aims to find a minimum operation to store all inbound plates while eliminating all blocking plates. We propose a novel integer programming model combining two moves in one time period. This model reduces the number of periods, thereby decreasing the model size, but requires extra constraints to avoid infeasible patterns. An exact branch-and-cut algorithm is introduced to tackle the influence of these extra constraints. This paper provides a new modeling approach for stack-related problems, and the experiments show that the proposed method outperforms other ILP-based methods in the literature.

Integer linear programming-based optimization methodology for reliability and energy-aware high-level synthesis

Continuous decrease in the transistor technology sizes has enabled much denser packaging of electronic components on chips, which has resulted in integrated circuits with lower costs and area. However, it has also given rise to new issues and challenges in the process of integrated circuit design, including higher vulnerability to soft errors. Modular hardware redundancy is a popular method for improving the reliability of a system against errors at a cost of increasing area and energy consumption. Voltage scaling methods can be employed to tackle high energy costs; however, this also negatively affects the circuit’s reliability and performance. Therefore, designing circuits with all these conflicting parameters is a very challenging task. In this study, we propose integer linear programming (ILP)-based high-level synthesis (HLS) methods to optimize both reliability and/or energy under the area and latency constraints. Our models employ full and partial duplication to improve the system reliability as long as the area constraint permits. They also utilize voltage islands as the energy reduction method of choice. What makes this problem even more interesting and complex is the fact that we use different versions of the same resources that have different area, latency, reliability, and energy values. Although this affects the execution time of the proposed methods, it also gives us more design options. We compared and showed the effectiveness of our methods against a genetic algorithm-based one on several HLS benchmarks. The ILP-based methods return the optimum results most of the time under the given time limits.

Inferring tumor progression in large datasets.

Identification of mutations of the genes that give cancer a selective advantage is an important step towards research and clinical objectives. As such, there has been a growing interest in developing methods for identification of driver genes and their temporal order within a single patient (intra-tumor) as well as across a cohort of patients (inter-tumor). In this paper, we develop a probabilistic model for tumor progression, in which the driver genes are clustered into several ordered driver pathways. We develop an efficient inference algorithm that exhibits favorable scalability to the number of genes and samples compared to a previously introduced ILP-based method. Adopting a probabilistic approach also allows principled approaches to model selection and uncertainty quantification. Using a large set of experiments on synthetic datasets, we demonstrate our superior performance compared to the ILP-based method. We also analyze two biological datasets of colorectal and glioblastoma cancers. We emphasize that while the ILP-based method puts many seemingly passenger genes in the driver pathways, our algorithm keeps focused on truly driver genes and outputs more accurate models for cancer progression.

Efficient Provision of Service Function Chains in Overlay Networks Using Reinforcement Learning

Software-Defined Networking (SDN) and Network Functions Virtualization (NFV) technologies facilitate deploying Service Function Chains (SFCs) at clouds in efficiency and flexibility. However, it is still challenging to efficiently chain Virtualized Network Functions (VNFs) in overlay networks without knowledge of underlying network configurations. Although there are many deterministic approaches for VNF placement and chaining, they have high complexity and depend on state information of substrate networks. Fortunately, Reinforcement Learning (RL) brings opportunities to alleviate this challenge as it can learn to make suitable decisions without prior knowledge. Therefore, in this article, we propose an RL approach for efficient SFC provision in overlay networks, where the same VNFs provided by multiple vendors are with different performance. Specifically, we first formulate the problem into an Integer Linear Programming (ILP) model for benchmarking. Then, we present the online SFC path selection into a Markov Decision Process (MDP) and propose a corresponding policy-gradient-based solution. Finally, we evaluate our proposed approach with extensive simulations with randomly generated SFC requests and a real-world video streaming dataset, and implement an emulation system for feasibility verification. Related results demonstrate that performance of our approach is close to the ILP-based method and better than deep Q-learning, random, and load-least-greedy methods.

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

The Network-on-Chips is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generalized fault-tolerance topology generation problem, where the link or switch failures can happen, for application-specific network-on-chips (ASNoC). With a user-defined number, K, we propose an integer linear programming (ILP) based method to generate ASNoC topologies, which can tolerate at most K faults in switches or links. Given the communication requirements between cores and their floorplan, we first propose a convex-cost-flow based method to solve a core mapping problem for building connections between the cores and switches. Second, an ILP based method is proposed to allocate K+1 switch-disjoint routing paths for every communication flow between the cores. Finally, to reduce switch sizes, we propose sharing the switch ports for the connections between the cores and switches and formulate the port sharing problem as a clique-partitioning problem Additionally, we propose an ILP-based method to simultaneously solve the core mapping and routing path allocation problems when considering physical link failures only. Experimental results show that the power consumptions of fault-tolerance topologies increase almost linearly with K because of the routing path redundancy. When both switch faults and link faults are considered, port sharing can reduce the average power consumption of fault-tolerance topologies with K = 1, K = 2 and K = 3 by 18.08%, 28.88%, and 34.20%, respectively. When considering only the physical link faults, the experimental results show that compared to the FTTG algorithm, the proposed method reduces power consumption and hop count by 10.58% and 6.25%, respectively; compared to the DBG based method, the proposed method reduces power consumption and hop count by 21.72% and 9.35%, respectively.

The controller placement problem for robust SDNs against malicious node attacks considering the control plane with and without split-brain

In software-defined networking (SDN), the control plane is separated from the data plane. For scalability and robustness reasons, the logically centralized control plane is implemented by physically distributing different controllers throughout the network. The determination of the number and location of the SDN controllers is known as the controller placement problem (CPP). For given maximum switch-controller (SC) and controller-controller (CC) delays in the regular (failure-free) state, we aim to find a CPP solution that maximizes the control plane robustness against a given number of malicious node attacks. We describe an ILP-based method aiming to enumerate all CPP solutions that guarantee the existence of a data plane path from every switch to any controller if all other controller nodes are shut down (worst-case scenario). Then, for different malicious node attacks, based on node centrality metrics and corresponding to different attacker’s strategies, we evaluate the previous solutions to determine the ones that maximize the network robustness, considering the SDN control plane operating with or without split-brain. In the computational results, we compare the robustness and the average SC and CC delays of the best CPP solutions. Since a control plane with split-brain requires more controllers, the average SC and CC delays in the regular state of its CPP solutions are significantly better, on average. Concerning robustness, split-brain does not always provide the best robust CPP solutions due to its feature of requiring a minimum number of connected controllers (which must be over half of the total number of them) to be operational.

Full Coverage of Optimal Phasor Measurement Unit Placement Solutions in Distribution Systems Using Integer Linear Programming

Integer linear programming (ILP) has been widely applied to solve the optimal phasor measurement unit (PMU) placement (OPP) problem for its computational efficiency. Using ILP, a placement with minimum number of Phasor Measurement Units (PMUs) and maximum measurement redundancy can be obtained while ensuring system observability. Author response: please delete this above sentence. However, the existing ILP-based OPP methods does not guarantee full coverage of solutions to the optimization problem, which may sequentially results in suboptimal supervision of the system. In this paper, a hybrid ILP-based method is proposed to cover all solutions to the OPP problem without any omission. Comparing with the existing exhaustive searching methods, the proposed method is more computationally efficient, which makes finding all solutions in a large system a more feasible problem.

CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design

1-D gridded design is one of the most promising solutions that can enable the scaling to 10 nm technology node and beyond. Line-end cuts are needed to fabricate 1-D layouts, where two techniques are available to resolve the conflicts between cuts: 1) cut redistribution and 2) cut mask assignment. In this paper, we consider incorporating the two techniques to enable the manufacturing of cut patterns in 1-D gridded design. We consider both 2-mask case (double patterning is performed on the cuts) and 3-mask case (triple patterning is performed on the cuts). We first present an accurate integer linear programming (ILP) formulation that can solve the co-optimization of cut redistribution and mask assignment optimally. In addition, we propose efficient graph-theoretic approaches based on a novel integrated graph model and a longest-path-based refinement algorithm. Experimental results demonstrate that our graph-theoretic approaches are orders of magnitude faster than the ILP-based method and meanwhile it can obtain very comparable results. For 2-mask case, comparing with the method that solves mask assignment and cut redistribution optimally but separately, our graph-theoretic approach that solves the two tasks simultaneously can achieve $95.0{\times }$ smaller cost on average. We also extend our graph-theoretic approach to 3-mask case. Comparing with the method that reduces the 3-mask problem to 2-mask problem and solves it indirectly, our innovative approach that solves the problem directly based on a novel framework of identifying and solving 4-cliques can achieve 7.6% smaller cost on average.

Advanced Compressor Tree Synthesis for FPGAs

This work presents novel methods for the optimization of compressor trees for FPGAs as required in many arithmetic computations. As demonstrated in recent work, important key elements for the design of efficient but fast compressor trees are target-optimized 4:2 compressors as well as generalized parallel counters (GPCs). However, the optimization of a compressor tree for minimal resources using both compressors and GPCs has not been addressed so far. As this combined optimization is a non-trivial task, three methods are proposed to find best solutions for a given problem size: 1) a heuristic that obtains compressor trees with typically less resources and fewer stages than state-of-the-art heuristics, 2) an integer linear programming (ILP)-based methodology that finds optimal compressor trees using the fewest stages possible, 3) a combined approach that partially solves the problem heuristically to reduce the search space for the ILP-based method. In all methods, the cost for pipeline registers can be included. Synthesis experiments show that the proposed methods provide pipelined compressor trees with about 40 percent less LUTs compared to trees of 2-input adders at the cost of being about 12 ...20 percent slower.

Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems

In this paper, a four-stage method for synthesizing reconfigurable ASNoC topology is proposed for partially dynamically reconfigurable systems, where the topology is reconfigured dynamically at run-time along with the application's execution. Firstly, a simulated annealing based topology-aware integrated optimization framework is proposed to generate the proper schedule and floorplan of task modules. Secondly, based on the schedule and floorplan of task modules, an Integer Linear Programming (ILP)-based method and a heuristic method, are proposed to partition the communication requirements of the application into T time intervals. Thirdly, we explore the proper positions of switches in the floorplan for global communications. Finally, considering the reconfiguration costs between adjacent time intervals, the routing path allocation problem is solved for time intervals in an iterative procedure to generate fine-grained dynamically reconfigurable ASNoC topologies. Experimental results show that, compared to the random partition of communication requirements, the proposed heuristic method and ILP-based method can achieve 5.4% and 10.0% power consumption improvement, respectively. And, the reconfigurable ASNoC can achieve 31.6% power consumption improvement when compared with static ASNoC.

Learning Automata-Based Data Aggregation Tree Construction Framework for Cyber-Physical Systems

A high degree of energy efficiency and real-time for data transmission is required in cyber-physical systems (CPSs). Data aggregation is an efficient technique to conserve energy by reducing the amount of transmission data. To optimize real-time communication under constraints of power consumption and data aggregation performance of each node in CPS, this paper presents a learning automata (LA)-based degree-bounded bottleneck data aggregation tree (DBBDAT) construction framework to minimize the maximum delay on data aggregation trees with bounded degree, which is an NP-hard problem. We model the network of CPS as a connected weighted and directed graph to form a network of LA. Degree-bounded data aggregation trees are constructed first by the action selection of each automaton. Then, the action vector of each automaton is updated by linear reward-inaction learning algorithm, and at last DBBDAT is constructed based on a threshold. Simulation results show that our approach significantly outperforms integer linear programming (ILP)-based method in terms of time complexity. Compared with ILP-based method, it can obtain an optimal solution or a suboptimal solution with guaranteed approximation ratios, and can control the tradeoff between accuracy and cost by choosing appropriate learning rate and threshold. Its distributed implementation is simple and it can efficiently solve the problem for the sparse graph in practice.

Optimal and heuristic algorithms for constructing interference-free multicast trees subject to delay and energy constraints on wireless mesh networks

Due to the great concerns of environmental protection and the high rising of prices in oil, energy efficiency has become an important factor for designing network applications. In this paper, we study an optimisation problem which is concerned about how to construct an interference free multicast tree subject to delay and energy constraints on a multi-channel multi-radio wireless mesh network. Our objective is to maximise the number of mesh clients that can be included in the multicast tree. This problem is referred as the EDMRM problem. To solve it, we first propose an optimal algorithm on the basis of integer linear programming ILP for the EDMRM problem. Since the ILP-based method is only feasible for small-scale networks, we also provide a tabu-based heuristic algorithm for solving practical networks that consist of a large number of nodes. The experimental results show that our tabu-based heuristic can outperform the other previously proposed methods.

Yield‐driven design‐time task scheduling techniques for multi‐processor system on chips under process variation: a comparative study

Process variation has already emerged as a major concern in design of multi-processor system on chips (MPSoC). In recent years, there have been several attempts to bring variability awareness into the task scheduling process of embedded MPSoCs to improve performance yield. This study attempts to provide a comparative study of the current variation-aware design-time task and communication scheduling techniques that target embedded MPSoCs. To this end, the authors first use a sign-off variability modelling framework to accurately estimate the frequency distribution of MPSoC components. The task scheduling methods are then compared in terms of both the quality of the final solution and the computational complexity of the scheduling algorithm. Experimental results on a wide range of benchmarks show that ILP-based task scheduling technique, while guaranteeing the optimality of the solution, can be costly for large application task graphs. On the other hand, one-pass heuristic method is 795 times faster than ILP-based method on average, but is ineffective to find reasonable solutions in the case of large task graphs. Finally, metaheuristic approaches can produce near-optimal schedules within 1–2% of the optimal solutions on average, with up to 7.8 times faster execution time compared with ILP-based approach.

Modeling the routing and spectrum allocation problem for flexgrid optical networks

Flexgrid optical networks are attracting huge interest due to their higher spectrum efficiency and flexibility in comparison with traditional wavelength switched optical networks based on the wavelength division multiplexing technology. To properly analyze, design, plan, and operate flexible and elastic networks, efficient methods are required for the routing and spectrum allocation (RSA) problem. Specifically, the allocated spectral resources must be, in absence of spectrum converters, the same along the links in the route (the continuity constraint) and contiguous in the spectrum (the contiguity constraint). In light of the fact that the contiguity constraint adds huge complexity to the RSA problem, we introduce the concept of channels for the representation of contiguous spectral resources. In this paper, we show that the use of a pre-computed set of channels allows considerably reducing the problem complexity. In our study, we address an off-line RSA problem in which enough spectrum needs to be allocated for each demand of a given traffic matrix. To this end, we present novel integer lineal programming (ILP) formulations of RSA that are based on the assignment of channels. The evaluation results reveal that the proposed approach allows solving the RSA problem much more efficiently than previously proposed ILP-based methods and it can be applied even for realistic problem instances, contrary to previous ILP formulations.

Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures

Scheduling periodic tasks onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an Integer Linear Programming (ILP) based framework that maps a given task set onto an Heterogeneous Multiprocessor System-on-Chip (HMPSoC) architecture. Our framework can be used with several objective functions; minimizing energy consumption, minimizing cost (i.e., the number of heterogeneous processors), and maximizing reliability of the system under performance constraints. We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to maximize reliability. We illustrate the effectiveness of our approach through several experiments, each with a different number of tasks to be scheduled. We also propose two heuristics based on Earliest Deadline First (EDF) algorithm for minimizing energy under performance and cost constraints. Our experiments on generated task sets show that ILP-based method reduces the energy consumption up to 62% percent against a method that does not apply DVS. Heuristic methods obtain promising results when compared to optimal results generated by our ILP-based method.

Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems

In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is very complex with variable latency hardware, such as instruction cache memories, or, to a lesser extent, the line buffers usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. The difficulty in these cache-locking methods lies in obtaining a good selection of the memory lines to be locked into cache. In this paper, we propose an ILP-based method to select the best lines to be loaded and locked into the instruction cache at each context switch (dynamic locking), taking into account both intra-task and inter-task interferences, and we compare it with static locking. Our results show that, without cache, the spatial locality captured by a line buffer doubles the performance of the processor. When adding a lockable instruction cache, dynamic locking systems are schedulable with a cache size between 12.5% and 50% of the cache size required by static locking. Additionally, the computation time of our analysis method is not dependent on the number of possible paths in the task. This allows us to analyze large codes in a relatively short time (100KB with 10^6^5 paths in less than 3min).