III-V Devices Research Articles

Progress in Antimonide Based III-V Compound Semiconductors and Devices

Progress in Antimonide Based III-V Compound Semiconductors and Devices

Progress in Antimonide Based III-V Compound Semiconductors and Devices

In recent years, the narrow bandgap antimonide based compound semiconductors (ABCS) are widely regarded as the first candidate materials for fabrication of the third generation infrared photon detectors and integrated circuits with ultra-high speed and ultra-low power consumption. Due to their unique bandgap structure and physical properties, it makes a vast space to develop various novel devices, and becomes a hot research area in many developed countries such as USA, Japan, Germany and Israel etc. Research progress in the preparation and application of ABCS materials, existing problems and some latest results are briefly introduced.

Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

Integration of III-V and Si CMOS Devices by Molecular Beam Epitaxy

Heterogeneous integration of III-V devices on Si may realize high performance integrated circuits for analog and digital applications. Such integration provides the combined advantages of high volume production of Si-based electronic circuitry with superior high speed performance of III-V components. Various technologies have been implemented to achieve this, from pick and-place die transfer to full wafer bonding to direct growth of III-V's on Si, but all require the implementation of high-quality III-V epilayers on Si CMOS host substrates. This paper presents the current status of various efforts at IQE to realize III-V device performance on Si substrates using molecular beam epitaxy (MBE) crystal growth technology.

Integration of III-V and Si CMOS Devices by Molecular Beam Epitaxy

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PERFORMANCE COMPARISON OF SCALED III-V AND Si BALLISTIC NANOWIRE MOSFETs

This paper describes analysis and simulations of Si and III-V Gate-All-Around nanowire MOSFETS assuming ballistic or quasi-ballistic transport. It is found that either channel material can provide the higher saturation current depending on the oxide thickness. For effective oxide thickness above approximately 0.5nm, the higher electron velocity of III-V's outweighs the higher density of states available in the Si device associated with higher effective mass and valley degeneracy and result in higher current for the III-V device. However, materials with higher effective mass and valley degeneracy result in smaller on-resistance in ballistic limit. Depending on the gate oxide capacitance, valley degeneracy may influence the attainable saturation current in a positive or negative way.

Band-Structure Effects on the Performance of III–V Ultrathin-Body SOI MOSFETs

This paper examines the impact of band structure on deeply scaled III-V devices by using a self-consistent 20-band -SO semiempirical atomistic tight-binding model. The density of states and the ballistic transport for both GaAs and InAs ultrathin-body n-MOSFETs are calculated and compared with the commonly used bulk effective mass approximation, including all the valleys (, , and ). Our results show that for III-V semiconductors under strong quantum confinement, the conduction band nonparabolicity affects the confinement effective masses and, therefore, changes the relative importance of different valleys. A parabolic effective mass model with bulk effective masses fails to capture these effects and leads to significant errors, and therefore, a rigorous treatment of the full band structure is required.

Low angle forward reflected neutral beam source and its applications

As one of the many nano-device fabrication techniques employed in the semiconductor industry, neutral beams are being examined using various methods to solve possible charge-related problems that occur during device processing. This review introduces a neutral beam generated by surface neutralization of an ion beam using a low angle forward reflection technique and explains its application to various areas such as surface treatments and etching. The neutralization efficiency of an ion beam using a low angle forward reflection technique was approximately 99.7%. When a metal-oxide-semiconductor device was etched using a reactive neutral beam, it was confirmed that charge-related problems such as aspect-ratio-dependent etching and gate oxide charging could be removed using reactive neutral beam etching instead of conventional reactive ion etching. Neutral beams can be beneficial to other devices such as the III-V device and field emission device.

Direct Growth of III-V Devices on Silicon

ABSTRACTOur direct growth approach of integrating compound semiconductors (CS) and silicon CMOS is based on a unique silicon template wafer with an embedded CS template layer of Germanium (Ge). It enables selective placement of CS devices in arbitrary locations on a Silicon CMOS wafer for simple, high yield, monolithic integration and optimal circuit performance. HBTs demonstrate a peak current gain cutoff frequency ft of 170GHz at a nominal collector current density of 2mA/μm2. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.

Compound semiconductor MOSFETs

Enhancement mode, high electron mobility MOSFET devices have been fabricated using an oxide high- κ gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga 2O 3, initially deposited on the surface of the III-V device unpins the GaAs Fermi level while a (Gd xGa 1−x) 2O 3 bulk ternary layer forms the highly resistive layer to reduce leakage current through the dielectric stack. A midgap interface state density of ∼2 × 10 11 cm −2 eV −1 and a dielectric constant of 20 are determined using electrical measurements.. N-channel MOSFETs with a gate length of 1 μm and a source-drain spacing of 3 μm show a threshold voltage, saturation current and transconductance of 0.11 V, 380 mA/mm and 250 mS/mm, respectively.

Photo-Dynamics of AlxGa1-xAs Heterostructure Dissolution: Experiments and Applications

We present the effects of the photo-assisted (532 nm) semiconductor dissolution on sidewall profile and etch rate for two different types of GaAs/AlGaAs laser heterostructure and two different etch masks. The experiments show that the photo-assisted dissolution characteristics (dissolution rate and side angle profile) strongly depend on the sample layer structure and mask conductivity. The experiments apply optical interference and photoluminescence techniques to determine the surface and photo-carrier dynamics. The research evaluates the application of photo-assisted semiconductor etching to the fabrication of III-V devices using 532 nm coherent illumination. The technique successfully produces vertical sidewalls and on-demand etch-stop layers in laser heterostructure using Sulfuric acid (H2SO4): Hydrogen peroxide (H2O2): DI water (H2O) etch system.

Key Issues for the Development of a Ge CMOS Device in an Advanced IC Circuit

Passivation of the channel in the gate stack is the most important problem for introducing another material than silicon into the channel of CMOS devices. In order to compare the mobility values of different passivation techniques, we propose to use a parameter, which is a proportional to the drive current of the transistor. We call this parameter the channel mobility value and it is calculated from the transistor equation. This channel mobility value can be used to benchmark more consistently the different passivation techniques on germanium or other semiconductor materials. A second issue for CMOS scaling on Ge is the poor performance of nMOS devices and there seems no solution in sight for this problem. Therefore we promote the investigation of technologies to allow the introduction of III-V materials on Ge to make nMOS devices in III-V devices complementary with Ge pMOS. A third key issue is the development of a manufacturable and low defect density germanium-on-insulator (GeOI) technology on 200mm and larger substrate sizes.

Digital III-Vs review

With the exception of specialised applications, III-V devices have not been the first choice for logic circuits. However, growing crisis could change this. The ability to crunch digital data at ever faster rates has been steadily delivered at reasonable cost by semiconductor devices since the late 1960s. In some senses, the delivery of technological advances has been too reliable, inflating expectations and resulting in periodic booms and busts.

Electrical Scanning Probe Microscopy: Investigating the Inner Workings of Electronic and Optoelectronic Devices

Semiconductor electronic and optoelectronic devices such as transistors, lasers, modulators, and detectors are critical to the contemporary computing and communications infrastructure. These devices have been optimized for efficiency in power consumption and speed of response. There are gaps in the detailed understanding of the internal operation of these devices. Experimental electrical and optical methods have allowed comprehensive elaboration of input–output characteristics, but do not give spatially resolved information about currents, carriers, and potentials on the nanometer scale relevant to quantum heterostructure device operation. In response, electrical scanning probe techniques have been developed and deployed to observe experimentally, with nanometric spatial resolution, two-dimensional profiles of the electrical resistance, capacitance, potential, and free carrier distribution, within actively driven devices. Experimental configurations for the most prevalent electrical probing techniques based on atomic force microscopy are illustrated with considerations for practical implementation. Interpretation of the measured quantities are presented and calibrated, demonstrating that internal quantities of device operation can be uncovered. Several application areas are examined: spreading resistance and capacitance characterization of free carriers in III-V device structures; acquisition of electric potential and field distributions of semiconductor lasers, nanocrystals, and thin films; scanning voltage analysis on diode lasers—the direct observation of the internal manifestations of current blocking breakdown in a buried heterostructure laser, the effect of current spreading inside actively biased ridge waveguide lasers, anomalously high series resistance encountered in ridge lasers—as well as in CMOS transistors; and free-carrier measurement of working lasers with scanning differential spreading techniques. Applications to emerging fields of nanotechnology and nanoelectronics are suggested.

Radiation Degradation of Nanomaterials

ABSTRACTWe have been developing a variety of nanomaterials for their use in power devices. An example of this is our use of both single wall carbon nanotubes and several varieties of semiconducting quantum dots (e.g., CuInS2, CdSe, InAs) for use in space solar cells. The ability of these materials to withstand the rigors of the space radiation environment will be essential for this intended application. In addition, we have also been developing both nanostructure III-V devices and radioluminescent quantum dots for use in radioisotope batteries. In this application these nanomaterials are subjected to an extremely high radiation level. Their degradation rate will be the key to determining the ultimate lifetime of these power supplies, which in principle can have an energy density that is orders of magnitude higher than any conventional battery chemistry. The nanomaterials included in this study were subjected to alpha particles fluences and the degradation in various properties were monitored using different analytical techniques. Specifically, the radioluminescence of the quantum dot intended for use in the radioisotope batteries was monitored as a function of fluence. In the case of the III-V quantum dots, their photoluminescent degradation as a function of fluence was measured in comparison to the bulk substrate on which the quantum dots were grown. Finally for the carbon nanotubes, relative intensities of the Raman peaks associated with their inherent vibrational modes was used to monitor the effects of the alpha radiation damage. Results on the radiation tolerance of these nanomaterials and its implication with regard to their ultimately utility in power devices are presented.

Accurate modeling of electron device I/V characteristics through a simplified large-signal measurement setup

Low-frequency dispersive phenomena due to self-heating and/or “traps” (that is, surface-state densities and deep-level traps) cause important dynamic deviations in the I/V characteristics of III-V devices and they must be taken into account when an accurate large-signal dynamic model is needed. To this end, different low-frequency dispersive I/V models have been proposed by the research community and, quite often, a characterization based on pulsed I/V measurement systems has been suggested as the most appropriate for the identification of model parameters. Unfortunately, besides requiring special-purpose setups, pulsed characterization may suffer from some drawbacks, as discussed in this article. As an alternative, a simple large-signal measurement setup is presented here, which is based on low-frequency sinusoidal excitations and can be easily implemented by means of conventional general-purpose laboratory instrumentation. The proposed setup is successfully adopted in this article to identify the dispersive I/V characteristics of a GaAs PHEMT large-signal model providing excellent prediction of intermodulation distortion at Ka-band frequencies. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2005.

SINGLE-EVENT EFFECTS IN III-V SEMICONDUCTOR ELECTRONICS

Single-event effects are a serious concern for high-speed III-V semiconductor devices operating in radiation-intense environments. GaAs integrated circuits (ICs) based on field effect transistor technology exhibit single-event upset sensitivity to protons and very low linear energy transfer (LET) particles. The current understanding of single-event effects in III-V circuits and devices, and approaches for mitigating their impact, are discussed.

Impact of dislocations on minority carrier electron and hole lifetimes in GaAs grown on metamorphic SiGe substrates

The minority carrier lifetime of electrons (τn) in p-type GaAs double heterostructures grown on GaAs substrates and compositionally graded Ge/Si1−xGex/Si (SiGe) substrates with varying threading dislocation densities (TDDs) were measured at room temperature using time-resolved photoluminescence. The electron lifetimes for homoepitaxial GaAs and GaAs grown on SiGe (TDD∼1×106 cm−2) with a dopant concentration of 2×1017 cm−3 were ∼21 and ∼1.5 ns, respectively. The electron lifetime measured on SiGe was substantially lower than the previously measured minority carrier hole lifetime (τp) of ∼10 ns, for n-type GaAs grown on SiGe substrates with a similar residual TDD and dopant concentration. The reduced lifetime for electrons is a consequence of their higher mobility, which yields an increased sensitivity to the presence of dislocations in GaAs grown on metamorphic buffers. The disparity in dislocation sensitivity for electron and hole recombination has significant implications for metamorphic III-V devices.

III-V Multi-Junction Materials and Solar Cells on Engineered SiGe/Si Substrates

ABSTRACTThe monolithic integration of high efficiency III-V compound solar cell materials and devices with lower-cost, robust and scaleable Si substrates has been a driving force in photovoltaics (PV) basic research for decades. Recent advances in controlling mismatch-induced defects that result from structural and chemical differences between III-V solar cell materials and Si using a combination of SiGe interlayers and monolayer-scale control of III-V/IV interfaces, have led to a series of fundamental advances at the material and device levels, which establish that the great potential of III-V/Si PV is within reach. These include demonstrations of GaAs epitaxial layers on Si that are anti-phase domain-free with verified dislocation densities at or below 1×106 cm−2 and negligible interface diffusion, minority carrier lifetimes for GaAs on Si in excess of 10 ns, single junction GaAs-based solar cells on Si with open circuit voltages (Voc) in excess of 980 mV, efficiencies beyond 18%, and area-independent PV characteristics up to at least 4 cm2. These advances are attributed in large part to the use of a novel “engineered Si substrate” based on compositionally-graded SiGe buffers such that a high-quality, low defect density, relaxed, “virtual” Ge substrate could be developed that can support lattice-matched III-V epitaxy and thus merge III-V technology based on the GaAs (or Ge) lattice constant with Si wafers. This paper focuses on recent results that extend this work to the first demonstration of high performance III-V dual junction solar cells on SiGe/Si. Open circuit voltages in excess of 2 V at one-sun have been obtained for the conventionally “lattice-matched” In0.49Ga0.51P/GaAs dual junction cells on inactive, engineered SiGe/Si; to our knowledge is the first demonstration of > 2V solar power generation on a Si wafer. Comparisons with identical cells on GaAs substrates reveal that the Voc on engineered Si retains more than 94% of its homoepitaxial value, and that at present both DJ/GaAs and DJ/SiGe/Si cells are similarly limited by current mismatch in these early cells, and not fundamental defect factors associated with the engineered Si substrates.

Evolution of T-shaped gate lithography for compound semiconductors field-effect transistors

T-shaped gate formation is a major processing step in the fabrication of high-performance FET-based III-V devices. Traditional bilayer or trilayer E-beam lithography methods using PMMA/(PMMA&PMAA) copolymers are high-cost options which also lack the required critical dimension control for manufacturing. Lithography methods that use only a single layer of PMMA for the formation of T-shaped gate stem, and routine I-line resist lithography for the tee-top, i.e., hybrid T-shaped gates, have been developed and extensively used in manufacturing. This approach has also been extended to the fabrication of deep submicron T-shaped gates using all I-line optical lithography. Both chemical shrinks and chromeless phase-shift resolution enhancement techniques have been investigated.