IF Filter Research Articles

High dynamic range 60 MHz powerline front-end IC

Presented for the first time, is a novel broadband powerline front-end realised in 0.25 µm SiGe BiCMOS with superior performance. The frequency range of the transmitter (TX) and the direct conversion receiver (RX) exceeds 60 MHz with a very wide dynamic range up to 99.5 dB for the lowest channel bandwidth. The integrated IF filter is tunable from 1 up to 8 MHz. The measured input-referred noise of the TX with low third intermodulation distortion (IMD3) is −140 and 144.5 dBm/Hz for the RX.

60 GHz multi-chip-module receiver with substrate integrated waveguide antenna and filter

A compact 60 GHz MCM receiver has been demonstrated by integrating millimetre-wave substrate-integrated waveguides and GaAs MMICs for the first time. The module includes a waveguide antenna and filter, MMIC LNA and mixer, and lumped elements for IF filtering embedded into the multilayer photo-imageable thick-film substrate. Cavities for MMIC attachment are photo-imaged as part of the standard process.

A CMOS TV tuner/demodulator IC with digital image rejection

Superheterodyne TV tuners have been implemented in discrete forms using tunable RF and SAW IF filters. Integrating TV tuners in CMOS technology without them is a challenging task to cope with technical issues such as harmonic mixing and image. The image rejection in low- or zero-IF systems has been limited to 30-40 dB by analog imperfections such as I/Q path gain and phase mismatches. A single-chip low-IF TV tuner solution is proposed so that the image can be suppressed digitally using an image cancellation technique based on a complex one-tap LMS signal decorrelation algorithm. Programmable digital filtering and video/sound demodulation make a multistandard TV tuner feasible in the 48-860 MHz VHF/UHF band. The chip has a maximum gain of 63 dB and an input automatic gain control (AGC) range from -15 to 25 dB with 0.85-dB steps. It achieves an image and IF rejection of 60 dB, a peak carrier-to-noise ratio (CNR) of 55 dB, and a peak sound signal-to-noise ratio (SNR) of 44 dB without frequency modulation (FM) de-emphasis. The prototype occupies 6/spl times/6 mm/sup 2/ in 0.25-/spl mu/m CMOS and consumes 1 W at 2.5 V.

Conversion of Analog TV Translators for DTV Operation

There are approximately 4700 TV translators in use today across the US and it is estimated that about 7-10 Million households receive their broadcast coverage through the use of these translators. As the transition to digital occurs, it will require the conversion of the existing analog translators to digital or the purchase of new digital translators. Where possible, the FCC has indicated that it is desired to add digital translator channels to co-exist with analog translators. In cases where new channels are not available, the more economic scenario to provide digital signal coverage is to convert the existing analog translators to digital operation (assuming the desired coverage and technical performance can be met) rather than purchase new equipment. This paper examines existing analog translator block diagrams and identifies areas of significant concern and/or weak links in the reception/transmission path. Guidelines for minimum performance levels for various portions of the RF block diagram are identified in order to meet a given Signal to Noise Ratio (SNR) level at the translator output. Typical low power translators of solid state design are characterized for DTV performance using modern test equipment. The amplitude and group delay performance of an analog receiver IF filter is examined to determine whether it is suitable for 8-VSB digital signals that are more spectrum efficient. Information on expected performance from heterodyne and demodulation/re-modulation (regenerative) translator configurations is presented with respect to impact on SNR and out-of-band emissions. A two-hop translator system is analyzed to view the impact of cascading distortions and some qualitative information is presented. Specific calculations are provided for adjacent channel scenarios. Specific measurements are made assuming a situation of equal power level incoming adjacent channel interference to determine the level of energy passed through a heterodyne translator. The measured results of typical analog translators converted to digital operation are used to evaluate a hypothetical site consisting of the converted analog translator that is co-located with analog transmitters occupying both adjacent channels. Associated digital power output levels are determined using Threshold of Visibility and Audibility (TOV and TOA) limits.

Frequency Responses of Surface-Acoustic-Wave Filters with Two-Track Slanted Finger Interdigital Transducers

In this study, the scattering characteristics of a novel surface-acoustic-wave (SAW) filter with two-track slanted finger interdigital transducers (SFITs) are investigated. The novel SAW filter consists of two-track input and output SFITs, with each track configured in many subfilters in parallel connection. Because the arrival time of a SAW may differ among subfilters, passband ripples appear. However, by properly controlling the gap length between the input and output SFITs of each track, passband ripples can be eliminated evidently. Moreover, due to differences in radiation conductance among subfilters, a curve fitting technique is used to design the overlap width of each subfilter to maintain the passband responses of the SAW filter as flat as possible. A Chebyshev polynomial and a two-step weighting technique are employed to decrease sideband level. Simulation results show that by tailoring SAW SFITs and the gap difference of each track, a high-performance broadband IF filter can be obtained.

Compensation of IQ imbalance and phase noise in OFDM systems

Nowadays, a lot of effort is spent on developing inexpensive orthogonal frequency-division multiplexing (OFDM) receivers. Especially, zero intermediate frequency (zero-IF) receivers are very appealing, because they avoid costly IF filters. However, zero-IF front-ends also introduce significant additional front-end distortion, such as IQ imbalance. Moreover, zero-IF does not solve the phase noise problem. Unfortunately, OFDM is very sensitive to the receiver nonidealities IQ imbalance and phase noise. Therefore, we developed a new estimation/compensation scheme to jointly combat the IQ imbalance and phase noise at baseband. In this letter, we describe the algorithms and present the performance results. Our compensation scheme eliminates the IQ imbalance based on one OFDM symbol and performs well in the presence of phase noise. The compensation scheme has a fast convergence and a small residual degradation: even for large IQ imbalance, the overall system performance for an OFDM-wireless local area network (WLAN) case study is within 0.6 dB of the optimal case. As such, our approach greatly relaxes the mismatch specifications and thus enables low-cost zero-IF receivers.

A 0.25-/spl mu/m CMOS quad-band GSM RF transceiver using an efficient LO frequency plan

This paper describes a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS applications. It is the most important design issue to maximize resource sharing and reuse in designing the multiband transceivers. In particular, reducing the number of voltage-controlled oscillators (VCOs) required for local oscillator (LO) frequency generation is very important because the VCO and phase-locked loop (PLL) circuits occupy a relatively large area. We propose a quad-band GSM transceiver architecture that employs a direct conversion receiver and an offset PLL transmitter, which requires only one VCO/PLL to generate LO signals by using an efficient LO frequency plan. In the receive path, four separate LNAs are used for each band, and two down-conversion mixers are used, one for the low bands (850/900 MHz) and the other for the high bands (1800/1900 MHz). A receiver baseband circuit is shared for all four bands because all of their channel spaces are the same. In the transmit path, most of the building blocks of the offset PLL, including a TX VCO and IF filters, are integrated. The quad-band GSM transceiver that was implemented in 0.25-/spl mu/m CMOS technology has a size of 3.3/spl times/3.2 mm/sup 2/, including its pad area. From the experimental results, we found that the receiver provides a maximum noise figure of 2.9 dB and a minimum IIP3 of -13.2dBm for the EGSM 900 band. The transmitter shows an rms phase error of 1.4/spl deg/ and meets the GSM spectral mask specification. The prototype chip consumes 56 and 58 mA at 2.8 V in the RX and TX modes, respectively.

Novel automatic tuning method of RC filters using a digital-DLL technique

A novel automatic tuning method for RC filters is proposed for CMOS low-IF transceivers. The method is based on a digital-DLL-like technique and tunes the time constant of filters automatically. The tuning range and the tuning accuracy are analyzed theoretically. To verify the method, a sixth-order 2-MHz IF filter for Bluetooth and a tuning circuit were fabricated in 0.18-/spl mu/m CMOS. The tuning circuit occupying 0.066 mm/sup 2/ includes only a reference first-order filter, a comparator, and a simple digital circuit. The measurement result of the filter and the tuning circuit shows that the maximum /spl plusmn/28% time-constant variation can be tuned within /spl plusmn/5% accuracy, which is consistent with theoretical results.

Design of Two-Track Surface Acoustic Wave Filters with Width-Controlled Reflectors

In this study, the frequency response of two-track surface acoustic wave (SAW) filters with width-controlled reflectors is investigated. The SAW filter consists of two tracks of input and output interdigital transducers (IDTs) and grating reflectors. With proper tailoring, the frequency response of the two-track SAW filter will only be dominated by the reflection characteristics of the reflectors. To achieve optimum performance, the Chebyshev polynomial is employed to calculate the line width distribution of the metal strips of the reflector. The period of the reflector is then adjusted to retain a symmetric response. Different stepwise weighting schemes are applied to recalculate the line width distribution for the realization of the modulated reflector. A novel transmission matrix method is proposed in this study for calculating the frequency responses of these devices. Simulation results show that a filter with high sidelobe suppression, low insertion loss, good shape factor and significantly small ripples in the passband region can be designed by properly tailoring the two-track SAW filter. The results obtained in this study can be employed to design IF filters applicable to the code division multiple access (CDMA) system.

Gigabit Wireless: System-on-a-Package Technology

The system-on-a-package (SOP) concept is considered as the solution of future communication modules, where more functionality, better performance, low cost, and more integrity is needed. We demonstrate how SOP technology can address the integration platform for future communication systems, especially gigabit wireless communications. After the introduction of the SOP concept, we introduce the critical design building blocks which are required in a viable SOP technology: integrated passives, embedded RF functions, including high-performance filters and baluns, and integrated antenna technologies. Second, we review how the three-dimensional deployment of core elements, such as baluns, lumped inductors, capacitors, and resistors, as well as IF or low-pass filters, enables RF-SOP module development. We demonstrate how advanced radio architectures, including direct conversion, antenna diversity, and collaborative signal processing, are enabled using the SOP technology format. Various ceramic and organic material based multilayer packaging technologies have been used for building such integrated modules as well as circuit blocks. The critical issues and challenges for developing advanced communication platforms using the SOP approach are discussed.

A 1-v 3.5-mW CMOS switched-opamp quadrature if circuitry for bluetooth receivers

A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and /spl Sigma//spl Delta/ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order /spl Sigma//spl Delta/ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass /spl Sigma//spl Delta/ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW.

A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-/spl mu/m CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm/sup 2/. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 /spl mu/s.

Design of withdrawal-weighted SAW filters.

This paper presents a new design algorithm for a withdrawal-weighted surface acoustic wave (SAW) transversal filter. The proposed algorithm is based on the effective transmission loss theory and a delta function model of a SAW transversal filter. The design process consists of three steps, which eventually determine eight geometrical design parameters for the filter in order to satisfy given performance specifications. First, the number of fingers in the input and output interdigital transducers (IDTs), plus their geometrical sizes is determined using the insertion loss specification. Second, the number and positions of the polarity reverses in the output IDT are determined using the bandwidth and ripple specifications. Third, the number and position for withdrawing and switching specific fingers in the output IDT and attached electrode area are determined to achieve the desired sidelobe level. The efficiency of the technique is illustrated using a sample design of an IF filter consisting of a uniform input IDT and withdrawal-weighted output IDT. The proposed algorithm is distinct from conventional techniques in that it can optimize the structural geometry of a withdrawal-weighted SAW filter in a direct manner by considering all the performance specifications simultaneously.

Reliability and Stability of Novel Tunable Thin Film

AbstractA new process has been developed in Paratek Microwave Inc. to formulate stable tunable (Ba, Sr)TiO3 (BST) based thin film material. Varactors, with a co-planar structure, were fabricated by using the new material. The varactor Q of 105 tested at 2 GHz was observed with average tunability of 58 % at 150V (37.5 V/μm). The lifetime tests indicated that this material is very stable under continuous 100 to 150 V dc bias both at the room temperature and in 70 °C environment. Thus, this novel tunable thin film material opens a new avenue to develop high quality tunable microwave devices. Tunable IF filters have been built by using this novel material for microwave backhaul radios and handset applications. Initial results of a RF phase shifter are also included and demonstrate another application of these films.

Time sidelobe reduction technique for binary phase coded pulse compression

AbstractA time sidelobe (TSL) reduction technique in binary code pulse compression is proposed. A code with a small peak sidelobe (PSL) is searched. Many codes have been obtained that have much smaller PSL than the conventional binary code with the compression ratio in the range from 5 to 16. Simulations are carried out for some of these codes and the optimum IF filter bandwidth is evaluated. It is confirmed that the waveform is stable for Doppler and the PSL value is kept small. © 2001 Scripta Technica, Electron Comm Jpn Pt 1, 84(12): 52–60, 2001

Very Small-Sized Resonator Filter Using Shear Horizontal Wave on Quartz

By composing interdigital transducers (IDTs) and reflectors consisting of films made of a heavy metal such as Au, Ta or W on an ST cut 90°X propagation (direction perpendicular to X-axis) quartz substrate, the authors realized a new type of shear horizontal (SH) wave. This wave has an excellent temperature characteristic, a large electromechanical coupling factor (k), and a large reflection coefficient at reflector electrodes. The square of this electromechanical coupling factor (k2=0.28∼0.34%) and the reflection coefficient at reflector electrodes are 2.2∼2.6 times and 30∼35 times, respectively, as large as those of a Rayleigh wave on an ST cut X propagation quartz substrate. The authors applied this technology to filters for the first intermediate frequency (first IF) stage of a global system for mobile communications (GSM) in the nominal center frequency from 200 to 400 MHz. As a result, we succeeded in developing the first IF filter having a low insertion loss, an excellent temperature characteristic (frequency shift: 1 ppm/°C) and a small package size (3×3 mm2), which is as small as a radio frequency (RF) surface acoustic wave (SAW) filter, for the first time.

A new generation of global wireless compatibility

The expanding growth of wireless communications has led to the proliferation of different standards. The highly competitive market demands low-cost, low-power, and small form-factor devices. This calls for the development of a single-chip, third-generation (3G) receiver capable of adapting to the various communications standards in a low-cost CMOS technology. However, fully integrated receiver architectures require the elimination of discrete high-Q image rejection and IF filters. Thus, the received signal is down-converted to baseband without channel filtering, which most frequently results in the presence of strong adjacent channel blockers along with the desired signal. Therefore, it is required from the baseband filter design to exhibit a high-dynamic range, a programmable bandwidth to accommodate different standards, precise tuning to select the desired channel within a standard, low power, and a small chip area. This article discusses the 3G wireless systems with a focus on the design of a reconfigurable baseband chain that precedes the ADC of a multistandard fully integrated wireless receiver. The baseband chain is adapted to accommodate the GSM, IS-95, and wideband CDMA wireless standards.

A single-chip RF front-end for the digital sound broadcasting

A complete single-chip RF front-end for the digital sound broadcasting has been developed. All RF circuits including LNAs, mixers, a PLL, a VCO, and an IF filter have been successfully integrated on a single-chip by employing the low-IF architecture.

A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers

A highly integrated 1.75-GHz 0.35-/spl mu/m CMOS transmitter is described. The I/Q modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer. The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and the use of a wide loop bandwidth PLL allowed for the complete integration of the synthesizers using low-Q components while achieving low phase noise. The entire transmit signal path from the digital-to-analog converters to the power amplifier, including two fully integrated frequency synthesizers, is integrated into a single-chip solution. The transmitter was tested with a testing buffer before the power amplifier (PA) and achieved less than 1.3/spl deg/ rms phase error when modulating a DCS-1800 GMSK signal. The prototype consumed 151 mA from a 3-V supply. A class-C PA, capable of driving 25 dBm off-chip, was included and the output was compared to the testing buffer with little change in the transmitter performance.

A 10.7-MHz CMOS SC radio IF filter using orthogonal hardware modulation

FM radio receivers require an IF filter for channel selection, customarily set at an IF center frequency of 10.7 MHz. Up until now, the limitations of integrated radio selectivity filters in terms of power dissipation, dynamic range, and cost are such that it is still required to use an external ceramic 10.7-MHz bandpass filter. This paper demonstrates a CMOS switched-capacitor IF filter that can be integrated with most of the rest of the FM receiver, eliminating external components and printed circuit board area. This is made possible through a combination of two techniques: orthogonal hardware modulation, and delta-charge redistribution. It exhibits a tightly controlled center frequency with a Q of 55 and also contains a programmable gain. The filter occupies an area of 0.7 mm/sup 2/ in a 0.6 /spl mu/m CMOS process with poly-poly capacitors. The new filter requires only 16 mW of power, and this is offset by elimination of the power needed in current designs to drive off-chip filters.