Id-Vg Characteristics Research Articles

Impact of Individual Charged Gate-Oxide Defects on the Entire $I_{D}$–$V_{G}$ Characteristic of Nanoscaled FETs

The measurement of the entire ID-VG characteristic of a nanoscaled pMOSFET before and after the capture of a single elementary charge in a gate-oxide defect is demonstrated. The impact of a single trapped carrier on the device characteristics is compared with 3-D atomistic device simulations. The ID-VG behavior is identified to depend on the location of the oxide defect with respect to the critical spot of the current percolation path in the channel.

Characteristics of Hot Hole Injection, Trapping, and Detrapping in Gate Oxide of Polycrystalline Silicon Thin-Film Transistors

The characterization and modeling of the hysteresis phenomenon observed in the off-state regime of n-channel polycrystalline thin-film transistors are presented. The shift in Id–Vg characteristics between upward and downward scan were measured under various bias conditions and ambient temperatures. The localized positive charge build-up induced by band-to-band hot hole injection is responsible for the mechanism for reducing the off-leakage current, and it is recovered through the thermal emission of trapped holes, which is enhanced by self-heating of the device during the on-current conduction. On the basis of this model, the internal device characteristics related to the thermal and oxide trap properties are analyzed.

Lateral I - Mos (Impact – Ionization) Transistor

One of the fundamental problems in the continued scaling of MOSFETs is the 60 mV/decade room temperature limit in sub-threshold slope. Therefore initial studies on a new kind of transistor, the I-MOS. is done. The I - MOS uses modulation of the breakdown voltage of a gated p - i - n structure in order to switch from the OFF to the ON state and vice versa. Since impact-ionization is an abrupt function of the electric field (or the carrier energy), simulations show that the device has a sub-threshold slope much lower than the above mentioned. This TCAD Sentaurus project simulates the electrical characteristics of an n-channel impact ionization metal-oxide-semiconductor (n-IMOS) transistor. The Id-Vg characteristics of a two dimensional (2D) n-IMOS structure are simulated. The Id-Vg characteristics are simulated for drain biases of 0 V and 1.1 V. In addition, various electrical parameters such as the breakdown voltage, the threshold voltage, the sub- threshold slope, and the on-current and off-current are extracted. Keywords - I-MOS,p-i-n structure,sub-threshold,threshold voltage,on current,off current

Monte Carlo Study of Ultimate Channel Scaling in Si and In$_{\rm 0.3}$Ga$_{\rm 0.7}$As Bulk MOSFETs

A detailed analysis of nonequilibrium electron transport in n-type Si and In0.3Ga0.7As MOSFETs scaled into ultimate limit of 5-nm gate length is carried out using ensemble Monte Carlo device simulations. The analysis is based on simulations of ID-VG characteristics for a template, 25-nm gate length Si MOSFET compared against previous results from various Monte Carlo device codes, and for an equivalent 25-nm gate length In0.3Ga0.7As MOSFET. The transistors are then laterally scaled from a gate length of 25 nm to 20, 15, 10 and 5 nm monitoring the average electron velocity, energy, and sheet density along the channel at a supply voltage of 1.0 V. A degradation of the injection velocity with the scaling of a gate/channel length is observed. While we have found a decrease in the overall electron velocity profile along the Si channel for gate lengths smaller than 10 nm and a decrease in the injection velocity from a gate length of 20 nm, the increase in the intrinsic drain current in the scaling process is continuous thanks to the increasing velocity at the drain side. However, the velocity in the InGaAs channel MOSFETs increases steadily during the scaling but the increase in the intrinsic drain current is less pronounced. This is the result of a source starvation, due to a low density of states in III-V semiconductors, which cannot provide a large enough electron sheet density in the channel. This effect is partially mitigated by the enhancement of density of states as a proportion of electrons in the source/drain transfers to upper valleys with a larger electron effective mass.

(Invited) Implications for Robust Reliability Testing of Power SiC MOSFETs

Threshold voltage (VT) instability remains an important issue for the performance, reliability, and qualification of large-area SiC power MOSFET devices. The direct application of existing reliability test standards to SiC power MOSFETs can in some cases result in an inconsistent pass/fail response for a given device. Significant variations in the ID-VGS characteristics, with accompanying shift in VT and change in leakage current, can result when these prescribed standards are applied as written. These variations are likely due to the complex time, temperature, and bias dependent nature of the charging and discharging of significant numbers of near-interfacial oxide traps that exists in as-processed SiC MOSFET devices. The significant increase in this VT instability at elevated temperature may suggest the activation of additional performance limiting oxide defects. If the negative shift in VT is large enough, it may increase the OFF-state drain leakage current and limit the long-term device reliability.

(Invited) Effect of Threshold-Voltage Instability on SiC Power MOSFET High-Temperature Reliability

A review of recent work on the effect of threshold-voltage instability on the reliability of SiC power MOSFETs is presented. Significant increases in the instability of the ID-VGS characteristics due to ON-state current stressing are similar in nature to increases caused by high-temperature bias stressing. Devices stressed by elevated temperature alone exhibited very little instability compared with devices stressed with both temperature and applied bias. These results, along with other results in the literature, suggest that this increase in threshold voltage instability at elevated temperature is due to the activation of additional near-interfacial gate oxide traps related to an O-vacancy defect known as an E′ center. It is important to develop improved processing methods to decrease the number of precursor oxide defect sites, since an increased negative shift can give rise to increased leakage current in the OFF-state and potential device failure if proper precautions are not met to provide an adequate margin for the threshold voltage.

Modeling of MFIS-FETs for the Application of Ferroelectric Random Access Memory

It is recognized that the conventional model for metal-ferroelectric-insulator-semiconductor field-effect transistors (MFIS-FETs) always neglects the history-dependent electric field effect of the ferroelectric layer. In this paper, an improved model combining the dipole switching theory with the silicon physics of metal-oxide-semiconductor structures and with Pao and Sah's double integral, respectively, is proposed to describe the capacitance-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) characteristics of MFIS structures and the drain current-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and drain current-drain voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) characteristics of MFIS-FETs. Close agreement between modeling and experimental results confirms the validity of the improved model. The influence of the gate voltage, SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer thickness, and interface layer thickness on the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> , and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> characteristics are simulated and discussed. The memory windows of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> characteristics, as well as the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> characteristics, increase with increasing gate voltage. The thicker the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or interface layer, the worse the transistor characteristics. This paper is expected to provide some guidance to the design and performance improvement of MFIS structure devices. In addition, the mathematical description can be easily combined with electronic design automation software for circuit simulation.

Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors

An efficient implementation of the density-gradient (DG) approach for the finite element and finite difference methods and its application in drift-diffusion (D-D) simulations is described in detail. The new, second-order differential (SOD) scheme is compatible with relatively coarse grids even for large density variations thus applicable to device simulations with complex 3-D geometries. Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using our SOD scheme can be accurately calibrated against Schrodinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids and the same results for very fine meshes. 3-D test D-D simulations using the finite element method are performed on two devices: a 10 nm gate length double gate metal-oxide-semiconductor field-effect transistor (MOSFET) and a 40 nm gate length Tri-Gate fin field-effect transistor (FinFET). In 3-D D-D simulations, the SOD scheme is able to converge to physical solutions at high voltages even if the previous schemes fail when using the same mesh and equivalent conditions. The quantum corrected D-D simulations using the SOD scheme also converge with an atomistic mesh used for the 10 nm double gate MOSFET saving computational resources and can be accurately calibrated against the results from non-equilibrium Green's functions approach. Finally, the simulated ID-VG characteristics for the 40 nm gate length Tri-Gate are in an excellent agreement with experimental data.

High-Temperature Reliability of SiC Power MOSFETs

We have observed a significant increase in the instability of SiC power MOSFET ID-VGS characteristics following bias stressing at elevated temperature, similar to the effect we previously observed following an ON-state current stress. Devices stressed by elevated temperature alone exhibited very little instability compared with devices stressed with both temperature and applied bias. These results, along with other results in the literature, suggest that this increase in threshold voltage instability at elevated temperature is due to the activation of additional near-interfacial oxide traps related to an O-vacancy defect known as an E′ center. It is important to develop improved processing methods to decrease the number of precursor oxide defect sites, since an increased negative shift can give rise to increased leakage current in the OFF-state and potential device failure if proper precautions are not met to provide an adequate margin for the threshold voltage.

Low-frequency noise behavior of tunneling field effect transistors

We report on the low-frequency noise (LFN) properties of tunneling field effect transistors (TFETs) fabricated on silicon-on-insulator substrate. Unlike conventional large FETs, where LFN obeys a 1/f frequency dependence, in large TFETs the LFN is dominated by random telegraph signal (RTS) noise characterized by 1/f2 slope. We explain this unique LFN behavior by the local junction control of the tunneling drain current, which involves few traps in a small area. The origin of RTS noise is corroborated by the gate length independence of the ID-VGS characteristics of TFETs. The relatively high amplitude of RTS noise in TFETs will have circuit design implications.

An analytical charge-based drain current model for nano-scale In0.52Al0.48As–In0.53Ga0.47 as a separated double-gate HEMT

In this paper, a two-dimensional electron gas (2DEG) charge-control model for carrier density in the channel is developed for a separated double-gate high-electron-mobility transistor. The model is extended to calculate Id–Vg characteristics of the device. The drain current model uses a polynomial dependence of sheet carrier concentration on the position of a quasi-Fermi energy level to predict the modulation of back carrier concentration due to a front gate bias. The characteristics are investigated for various channel thicknesses and delta doping concentrations in order to study the effect of the back gate on the overall device performance. The analytical results so obtained are verified by comparing them with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

Electron velocity decline in Si nanoscales MOSFETs with the shortening of gate length

The ensemble Monte Carlo device simulations are employed to obtain I-V characteristics for the 25 nm gate length template Si MOSFETs designed by the SiNANO consortium. The simulated ID-VG characteristics are compared against previous results from various Monte Carlo device codes [Fiegna C et al., in Proc. SISPAD 2007, pp. 57-60 (Springer Vienna, 2007)]. After this verification, we have scaled the transistor laterally only from a gate length of 25 nm to gate lengths of 20, 15, 10 and 5 nm. We have then monitored the average electron velocity and sheet density along the channel at a supply voltage of 1.0 V in order to gain an insight into the degradation of the injection velocity experimentally observed in various Si transistor architectures when the gate length is scaled into deep sub-50 nm dimensions. We have found a substantial decrease of the overall velocity profile along the channel including a decrease of the peak velocity when the channel is smaller than 15 nm while the drive current is able to sustain its increase thanks to the increasing velocity at the drain side.

Effect of interface state trap density on the performance of scaled surface channel In0.3Ga0.7 As MOSFETs

The effect of interface state trap density, Dit, on the ID-VG characteristics of scaled surface channel MOSFETs based on In0.3 Ga0.7 As channel has been investigated using drift-diffusion simulations. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current when these devices are scaled from a gate length of 65 nm to 35 nm, 25 nm and 18 nm. The distributions of interface states having high density tails that extend into the conduction band can significantly impact the subthreshold performance of the larger gate length device. Furthermore, the same distributions have smaller impact on the performance of shorter channel devices which were designed with smaller high-κ thickness.

Effects of Si implantation on the total dose hardness of fully-depleted SIMOX wafers

Total dose hardened fully-depleted SOI materials are fabricated on separation by implanted oxygen (SIMOX) materials by silicon ion implantation and annealing. The ID–VG characteristics of pseudo-MOS transistors pre- and post-irradiation are tested with 60Co gamma rays. The chemical bonds and the structure of Si in the buried oxide are also studied by X-ray photoelectron spectroscopy and cross-sectional high-resolution transmission electron microscopy, respectively. The results show that Si nanocrystals in the buried oxide produced by ion implantation are efficient deep electron traps, which can significantly compensate positive charge buildup during irradiation. Si implantation can enhance the total-dose radiation tolerance of the fully-depleted SOI materials.

Lateral Trapped-Charge Profiling Based on the Extraction of the Flatband Voltage by Using the Optical Substrate Current in Nitride-Based Charge-Trap Flash Memories

A lateral charge-profiling technique based on local-flatband-voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> )monitoring using optical-substrate-current spectroscopy (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Sub,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">photo</sub> spectroscopy) in nitride-based charge-trap flash (CTF) memories is proposed. Under optical illumination by photons with above-bandgap energy E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ph</sub> (>E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g,Si</sub> ), I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Sub,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">photo</sub> is abruptly increased at the gate voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> due to a sudden increase of the excess minority-carrier diffusion current. As expected in this principle, while the single-step feature of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Sub,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">photo</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> curve is observed in the case of N-MOSFETs, a multistep response is clearly observed in nitride-based CTF memories. The mechanism of steplike I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Sub,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">photo</sub> spectroscopy is analyzed, supported by analytical models, and verified by comparison with TCAD simulation results. The results show that the height of the step corresponds to the lateral length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TC</sub> of the region, over which localized trapped charges are distributed, and its width to the density Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nit</sub> (x)=qN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nit</sub> (x) [C/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ] in the nitride storage layer. Based on the proposed I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Sub,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">photo</sub> spectroscopy, lateral charge profiling is demonstrated in a programmed NROM cell. The validity of the proposed I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Sub,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">photo</sub> spectroscopy is confirmed by comparing the measured I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> characteristics with TCAD simulation incorporating the extracted N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nit</sub> (x) by I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Sub,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">photo</sub> spectroscopy. The proposed lateral charge-profiling technique is expected to be a useful technique for extracting the trapped-charge distribution in NROM and/or multibit CTF memories. This extraction technique has advantages of electrical stress free, exclusion of the effect from interface traps, and the applicability to devices with large gate leakage current.

Analysis of Pentacene Field-Effect Transistor with a Ferroelectric P(VDF–TeFE) Gate Insulator as an Element of Maxwell–Wagner Effect System

Analysis of pentacene field-effect transistors (FETs) with a ferroelectric gate insulator, i.e., a copolymer of vinylidene fluoride and tetrafluoroethylene [P(VDF–TeFE)], as an element of Maxwell–Wagner system revealed that the turnover of spontaneous polarization in P(VDF–TeFE) modulated the amount of charge injected from the source electrode and accumulated in the FET channel. This analysis well accounted for the hysteresis behavior observed in the Ids–Vgs characteristics. Pentacene FETs using polyimide gate insulator also showed a similar hysteresis behavior in the Ids–Vgs characteristics, but that the results were caused by carrier injection from the gate electrode into the polyimide gate insulator.

Trapping in 1nm EOT high-k / MG

PFET's with EOT ~1 nm shows a large hysteresis at high field in the Id-Vg characteristics, while nothing is sensed for nmos devices. An advanced charge pumping technique proves that this hysteresis in pmos is caused by hole traps in the high-k. Furthermore, we show how NBTI defects are affected correlated with such hole traps. We will demonstrate how optimization of the nitridation process can strongly reduce the hole trap density. Phase separation in the HfSiON can be detected by this simple hole trap measurements.

Inversion-Mode Self-Aligned $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor With HfAlO Gate Dielectric and TaN Metal Gate

A high-performance In0.53Ga0.47As n-channel MOSFET integrated with a HfAlO gate dielectric and a TaN gate electrode was fabricated using a self-aligned process. After HCl cleaning and (NH4)2S treatment, the chemical vapor deposition HfAlO growth on In0.53Ga0.47As exhibits a high-quality interface. The fabricated nMOSFET with a HfAlO gate oxide thickness of 11.7 nm shows a gate leakage current density as low as 2.5 times 10-7 A/cm2 at Vg of 1 V. Excellent inversion capacitance was illustrated. Silicon implantation was self-aligned to the gate, and low-temperature activation for source and drain was achieved by rapid thermal annealing at 600degC for 1 min. The source and drain junction exhibited an excellent rectifying characteristic and high forward current. The result of an In0.53Ga0.47As nMOSFET shows well-performed Id-Vd and Id-Vg characteristics. The record high peak electron mobility of 1560 cm2/Vs has been achieved without any correction methods considering interface charge and parasitic resistance.

Self-aligned inversion-type enhancement-mode GaAs metal-oxide-semiconductor field-effect transistor with Al2O3 gate dielectric

In this letter, we report fabrication of self-aligned inversion-type enhancement-mode GaAs metal-oxide-semiconductor (MOS) field-effect transistors with atomic layer deposition of Al2O3 gate dielectric directly on GaAs substrates using a simple ex situ wet clean of GaAs. Thermal stability of the gate stack was examined by monitoring the frequency dispersion behavior of GaAs MOS capacitors under different annealing conditions. A maximum drive current of ∼4.5μA∕μm was obtained for a gate length of 20μm at a gate overdrive of 2.5V. The threshold voltage and subthreshold slope were determined to be ∼0.4V and ∼145mV∕dec from the corresponding Id-Vg characteristics.

Analysis of Charge Accumulation in Pentacene Feld Effect Transistor with Ferroelectric Gate Insulator using Maxwell–Wagner Model

Pentacene field-effect transistors (FETs) with a ferroelectric gate insulator [P(VDF–TeFE)] were investigated to clarify the relationship between the behavior of injected carriers and dipolar polarization. Prepared samples showed a hysteresis behavior in the Ids–Vgs characteristics, because the amount of carriers accumulated at the channel changes in accordance with the spontaneous polarization of P(VDF–TeFE) films. However, the observed threshold voltage shift was smaller than expected one, and Igs–Vgs characteristics were not dependent on the channel length. These results show that the turn over of the spontaneous polarization occurs only in the channel region close to the source and drain electrodes.