Hybrid Technology Multi-Threaded Research Articles

High performance Nb Josephson devices for petaflops computing

The Hybrid Technology Multi-Threaded (HTMT) approach to petaflops computing includes large numbers of ultra-high performance Nb Rapid Single Flux Quantum (RSFQ) processor and memory chips, making it by far the largest active superconducting electronics project in the United States. In order to achieve petaflops, RSFQ circuits with 10/sup 5/ to 10/sup 6/ junctions per chip will be required to operate at clock speeds of 50 to 100 GHz, far beyond the current state of the art. In this paper, we review the state of the art of Nb circuit fabrication and discuss the requirements for significantly improving circuit density and speed.

COOL MULTITHREADING IN HTMT SPELL-1 PROCESSORS

A COOL-1 multiprocessor shared memory system based on superconductor Rapid Single-Flux Quantum (RSFQ) technology is being developed at SUNY (Stony Brook, USA) within the framework of the Hybrid Technology Multithreaded architecture (HTMT) petaflops project led by JPL. This paper describes a multithreading approach proposed in the COOL-I architecture and mechanisms to exploit the thread level parallelism in RSFQ processors called SPELL-1. Up to 128 fine-grain threads called (instruction) streams arranged in 16 groups of 8 streams each can run in parallel within a SPELL-1 processor. All eight streams comprising each COOL stream cluster can communicate and synchronize directly via shared registers. Fast creation and termination of streams including speculative stream execution are also supported.

COOL Multithreading in HTMT SPELL-1 Processors

A COOL-1 multiprocessor shared memory system based on superconductor Rapid Single-Flux Quantum (RSFQ) technology is being developed at SUNY (Stony Brook, USA) within the framework of the Hybrid Technology Multithreaded architecture (HTMT) petaflops project led by JPL. This paper describes a multithreading approach proposed in the COOL-I architecture and mechanisms to exploit the thread level parallelism in RSFQ processors called SPELL-1. Up to 128 fine-grain threads called (instruction) streams arranged in 16 groups of 8 streams each can run in parallel within a SPELL-1 processor. All eight streams comprising each COOL stream cluster can communicate and synchronize directly via shared registers. Fast creation and termination of streams including speculative stream execution are also supported.

Full-scale integration of superconductor electronics for petaflops computing

Ultralow-power and ultrahigh-speed single-flux-quantum electronics is an enabling technology solution for near-term petaflops computing. The proposed hybrid technology multithreaded (HTMT) petaflops-scale computer architecture includes computational modules operating at 100 GHz and an I/O throughput of 32 Pbits s-1. In this frequency regime, on-chip interconnect mimics the system interconnect problem. On-chip latency can be minimized with increased gate density by using more levels of metal and smaller line pitch. This may be even more important than increasing the maximum clock rate by using smaller junctions and higher critical current density. Superconductor ICs at an integration level of 100k gates cm-2 are proposed for the processors, first-level cache and interprocessor network. Petaflops capacity will require a compact, optimized system-level packaging strategy to achieve the necessary computational density and interconnect bandwidth. Modular packaging and automated circuit testing are required to minimize manufacturing costs. We focus on the critical technology challenges that exist for the IC foundry, packaging and the I/O data link and present technology roadmaps to achieve the HTMT requirements.

Manufacturability of superconductor electronics for a petaflops-scale computer

Ultra-low power and ultra-high speed single-flux-quantum electronics is an enabling near-term technology solution for petaflops-scale computers. The proposed Hybrid Technology Multi-threaded (HTMT) petaflops computer architecture includes computational modules operating at 100 GHz and an I/O throughput of 32 Petabits/s. Due to fundamental time-of-flight and power dissipation limitations of semiconductor ICs, superconductor ICs at an integration level of 100 k gates/cm/sup 2/ are proposed for the HTMT computation modules. In this paper, we discuss the manufacturability of superconductor-based computation modules, including the IC foundry process, packaging, and data link out of the cryopackage. We focus on the critical technical challenges that exist in each of these areas and present a technology roadmap to achieve the HTMT requirements.

CNET: design of an RSFQ switching network for petaflops-scale computing

This work is part of a project to design a petaflops-scale computer using a Hybrid Technology Multi-Threaded (HTMT) architecture. In the core of the superconductor part of the HTMT system there should be a high-bandwidth low-latency RSFQ switching cryonetwork (CNET) connecting 4.096 computing modules with each other and with room-temperature semiconductor components. In this report, we present a preliminary study of three simplified, "flat" models of the CNET, each for two alternative architectures: banyan network and pruned high-dimensional mesh. The results indicate that with the speed and space limitations accepted in the HTMT concept, CNET will be able to provide a cross-sectional bandwidth of about 2/3 packets per computing module per network clock cycle (in the present design, 32 ps).

Adapting to Hostile Architectural Environments

Adapting to Hostile Architectural Environments