Hybrid Logic Research Articles

Hybrid Logic of the Hide and Seek Game

Hybrid Logic of the Hide and Seek Game

Realistic Realizability: Specifying ABIs You Can Count On

The Application Binary Interface (ABI) for a language defines the interoperability rules for its target platforms, including data layout and calling conventions, such that compliance with the rules ensures “safe” execution and perhaps certain resource usage guarantees. These rules are relied upon by compilers, libraries, and foreign-function interfaces. Unfortunately, ABIs are typically specified in prose, and while type systems for source languages have evolved, ABIs have comparatively stalled, lacking advancements in expressivity and safety. We propose a vision for richer, semantic ABIs to improve interoperability and library integration, supported by a methodology for formally specifying ABIs using realizability models. These semantic ABIs connect abstract, high-level types to unwieldy, but well-behaved, low-level code. We illustrate our approach with a case study formalizing the ABI of a functional source language in terms of a reference-counting implementation in a C-like target language. A key contribution supporting this case study is a graph-based model of separation logic that captures the ownership and accessibility of reference-counted resources using modalities inspired by hybrid logic. To highlight the flexibility of our methodology, we show how various design decisions can be interpreted into the semantic ABI. Finally, we provide the first formalization of library evolution, a distinguishing feature of Swift’s ABI.

Games for hybrid logic from semantic games to analytic calculi

Abstract Game semantics and winning strategies offer a potential conceptual bridge between semantics and proof systems of logics. We illustrate this link for hybrid logic—an extension of modal logic that allows for explicit reference to worlds within the language. We lift a Hintikka-style semantic game to a disjunctive game. The disjunctive game adequately models entailment and validity over classes of frames characterizable in the hybrid language. The search for winning strategies in this game can be reformulated as a sequent-style proof system.

Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUT

This paper analyzes the efficiency of different FPGA architectures consisting of Hybrid logic blocks (HLB) formed with Look-up Tables (LUTs) and Universal Logic Gates (ULGs). Pure LUT-based architectures induce area overhead and a longer delay. A ULG is designed to realize an efficient architecture compared to pure LUT-based architectures. Using this ULG and LUT in different proportions, HLBs are designed. The Field Programmable Gate Array (FPGA) architectures containing these proposed HLB structures are analyzed using various Microelectronics Centre of North Carolina (MCNC) benchmark circuits and compared with the performance of the existing designs. The result shows that the proposed architecture design can save a tremendous amount of time in overall flow and routing along with area improvements.

A review of graph neural networks and pretrained language models for knowledge graph reasoning

Knowledge Graph (KG) stores human knowledge facts in an intuitive graphical structure but faces challenges such as incomplete construction or inability to handle new knowledge. Knowledge Graph Reasoning (KGR) can make KGs more accurate, complete, and trustworthy to support various artificial intelligence applications better. Currently, the popular KGR methods are based on graph neural networks (GNNs). Recent studies have shown that hybrid logic rules and synergized pre-trained language models (PLMs) can enhance the GNN-based KGR methods. These methods mainly focus on data sparsity, insufficient knowledge evolution patterns, multi-modal fusion, and few-shot reasoning. Although many studies have been conducted, there are still few review papers that comprehensively summarize and explore KGR methods related to GNNs, logic rules, and PLMs. Therefore, this paper provides a comprehensive review of GNNs and PLMs for KGR based on a large number of high-quality papers. To present a clear overview of KGR, we propose a general framework. Specifically, we first introduce the KG preparation. Then we provide an overview of KGR methods, in which we categorize KGR methods into GNNs-based, logic rules-enhanced, and pre-trained language models-enhanced KGR methods. Furthermore, we also compare and analyze the GNN-based KGR methods in two scenarios. Moreover, we also present the application of KGR in different fields. Finally, we discuss the current challenges and future research directions for KGR.

Research on Hybrid Logic Dynamic Model and Voltage Predictive Control of Photovoltaic Storage System

This paper investigates microgrid systems characterized by the coexistence of discrete events and continuous events, a typical hybrid system. By selecting the charging and discharging processes of the energy storage unit as logical variables, a mixed logical dynamic (MLD) model for the microgrid in islanded mode is established. Based on this model, model predictive control (MPC) theory is employed to optimize the energy management strategy, aiming to stabilize the DC bus voltage of the photovoltaic (PV) unit and minimize the switching frequency of the energy storage unit’s charging and discharging processes during system operation.

Hybrid Logics and Mediating Devices: Accounting Calculations in the Organisation of Pharma R&D

Hybrid Logics and Mediating Devices: Accounting Calculations in the Organisation of Pharma R&D

The Strategic Evolution of Institutional Logics Across Social Entrepreneurial Process: A Multiple Case Study

Abstract Although a hybrid logic is widely recognized as the best institutional logic for social enterprises, why and how such a hybrid logic works for social enterprises is under-explored. Based on the institutional logic theory, we conduct a multiple-case study to investigate how and why the two competing logics are combined to form a hybrid logic during social entrepreneurial process. Data are collected from the in-depth semi-structured interviews with social entrepreneurs from three leading social enterprises in China. We categorize a hybrid logic model as a dominant logic model, which includes a social-dominant logic model and a commercial-dominant logic model, and an equality of dual logic model. We find that the adoption of a hybrid logic is affected by the type of a social enterprise and the motivation to acquire different legitimacy. Specifically, an integrated social enterprise adopts a commercial-dominant logic model while an external social enterprise employs a social-dominant logic model to achieve sustainability. An embedded social enterprise can adopt an equality of dual logic model from its establishment. Our study contributes to research on strategic social entrepreneurship by revealing the dynamic relationship among different types of social enterprises, the adoption of a hybrid logic at different entrepreneurial stages, the motivation to acquire different legitimacy, and business outcomes.

Design of low delay low power hybrid logic based flip-flop using FinFET

The need for a low-power and high-speed technology for computation of digital signals is rising due to the fast growth of technological innovations. Flip-flops serve as fundamental elements in signal processing technologies. Hybrid logic has great potential for constructing flip-flop circuits because of its minimal transistor count as well as low-power properties.The present investigation presents a design for a tiny and low-power hybrid flip-flop that operates fully statically. The design has been developed by utilizing different circuitry-reduction techniques. It incorporates a hybrid logic approach combining pass transistor logic to decrease circuit complexity. The ongoing work utilizes a hybrid logic with low delay and low power to generate flip-flops. The proposed flip-flop design significantly decreases latency compared to the existing master-slave flip-flops. This flip-flop remains immune to clock overloading, resulting in reduced power consumption. Reducing the quantity of PFET (P-channel Field Effect Transistor) transistors enhances the circuit's delay, area, and power consumption. Implementing these circuit optimization techniques yields several benefits, such as reduced CLOCK-to-OUT and DIN-to-OUT node delays, decreased average power consumption, lower leakage power, and a transistor count of only 18. The results were achieved using Cadence Virtuoso at 18 nm finFET technology, with varied process corners, supply voltages ranging from 0.7 V to 1 V, and temperatures ranging from -50 °C to 75 °C. This study also presents a Monte Carlo simulation of power consumption, leakage, and delay for the suggested flip-flop. According to the simulations, the recommended flip-flop exhibits exceptional stability. The recommended flip-flop has lower power usage by at least 17.95 % compared to standard architectures due to the lower number of PFET transistors.

The Opto‐Ionic Voltage Effect Soft Triode: An Optical‐To‐Ionic Signal Converter

AbstractA novel opto‐ionic device based on the recently reported Ionic Voltage Effect Soft Triode (IVEST) is introduced. This device can convert optical to ionic signals as it is shown here. The characterization of the opto‐IVEST points to an optically induced charging mechanism and to various potential applications. The opto‐IVEST shows the ability to detect and memorize optical signals. Furthermore, the device exhibits learning behavior and a hybrid logic gate function.

Completeness of tableau calculi for two-dimensional hybrid logics

Completeness of tableau calculi for two-dimensional hybrid logics

Theorizing the Third Generation of Fashion Designers: The Case of Pharrell Williams at Louis Vuitton

This article delves into the implications of celebrity-driven fashion brands in the 21st century. Initially, it traces the evolution of the first generations of traditional fashion designers from the 19th and 20th centuries, highlighting how designers serve as a simplified reference point, as they aggregate the intricate processes of fashion creation under a public persona. Subsequently, employing a close reading and visual analysis methodology, I examine the case of musician Pharrell Williams in his role as creative director at Louis Vuitton. I argue that celebrities taking on roles as fashion designers represent a new generation in this field. This shift is an inevitable culmination of the “celebrification” that traditional designers have undergone over the years. I further argue that celebrity-driven brands introduce a diverse offering in terms of taste, experience and image. By integrating fashion with entertainment, celebrities enable brands like Louis Vuitton to reorganize as a “Cultural Maison.” These celebrities, outsiders penetrating high-end fashion, exploit the so-called democratic and hybrid logic of social media, and gradually overshadowing the cultural significance of traditional designers, pushing them behind the scenes. This shift challenges and may even redefine our understanding of what constitutes the cultural role of fashion designers.

Symmetric and conflated intuitionistic logics

Abstract Two new propositional non-classical logics, referred to as symmetric intuitionistic logic (SIL) and conflated intuitionistic logic (CIL), are introduced as indexed and non-indexed Gentzen-style sequent calculi. SIL is regarded as a natural hybrid logic combining intuitionistic and dual-intuitionistic logics, whereas CIL is regarded as a variant of intuitionistic paraconsistent logic with conflation and without paraconsistent negation. The cut-elimination theorems for SIL and CIL are proved. CIL is shown to be conservative over SIL.

Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively.

Pioneering Security: A Hybrid Logic Framework for the Future of IoT Protection

In a complicated situation, the Internet of Things simplifies the process of connecting a wide range of things. Because of its openness and lack of human control, the Internet of Things is open to assaults like denial of service (DoS) and man-in-the-middle attacks. Furthermore, any device that can connect to the internet may be hacked. These attacks put the network connections and the actual equipment at danger. IoT security and privacy will so be compromised. Due to its limited power, bandwidth, and storage, the Internet of Things requires a security solution that does not overload it. This study aims to preserve consumers' trust in the Internet of Things (IoT) by safeguarding their data against unauthorised access and maintaining the privacy of their personal information. With the ultimate objective of presenting a unique hybrid and optimised lightweight logical security architecture to ensure data privacy and integrity while making effective use of available resources, all research are carried out with this purpose in mind. The Hybrid Lightweight Security Framework (HLSF), which this study suggests, offers secrecy and integrity in addition to authentication. The structure consists of three distinct steps. The first step is registration, the second is authentication, and the third is transit security, which protects data while it is being transported. Compared to other current frameworks, the results reveal that HLSF performs better in terms of precision, recall, and accuracy when applied to an IoT situation.

Design a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency and high-speed

Design a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency and high-speed

Compact hybrid silicon nitride and lithium niobate nano-film photoelectronic reversible logic gate

Photoelectronic hybrid logic operation improves digit circuit efficiency without any additional photoelectric conversion, especially a photoelectronic reversible logic gate may reduce energy dissipation. In this paper, a compact photoelectronic reversible logic gate is proposed based on a hybrid silicon nitride and lithium niobate nano-film waveguide. Tow Mach-Zehnder modulators are cascaded together to construct the main part of the compact photoelectronic reversible logic gate. The whole length of the gate is only 4.4mm, one hundredth of the length of the common proton exchange lithium niobate modulator. By operating at the wavelength of 1.55μm, the proposed Mach-Zehnder modulator only requires 4.9V voltage to complete a full cross-coupling, which is well compatible with CMOS technology. It is demonstrated that at the wavelength range of 1.4μm to 1.6μm, the average insertion loss is 0.6dB, the minimum crosstalk is -47dB, and the maximum extinction ratio is 41dB; in the voltage range of 4V to 6V, the average insertion loss is 0.63dB, the minimum crosstalk is -26dB, and the maximum extinction ratio is 22dB. These features indicate that the photoelectronic reversible logic gates have good performances, bringing the photoelectronic logic gates into a new design parameter space and providing a possible solution for easing the electronic bottleneck.

WITHDRAWN: Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

In this paper, we propose a hybrid full-swing adder (HFSA) circuit that uses the hybrid full-swing logic (HFSL) technique, which consists of 20 transistors. This circuit relies heavily on a 12-transistor XOR-XNOR circuit to optimize the area and power. Our novel XOR-XNOR circuit plays a crucial role in achieving high-efficiency HFSA circuits. It integrates 2-to-1 multiplexers, pass transistor logic, and inverters to deliver glitch-free full-swing outputs. We compared the efficiency and practicality of our design with those of 10 alternatives by considering their performances and characteristics. Our novel XOR-XNOR circuit surpassed its counterparts with an exceptional chip area reduction of 14.14–28.01 %, an average power of 2.44 μW, and remarkably low delays of 25.88 and 24.87 ps. Notably, the proposed full adder achieved a chip area reduction of 11.30–49.69 %, 3.582 μW power, and a 72.66 ps delay. It emphasizes large-scale structures, such as 4-bit to 64-bit full adders, implemented using cascaded designs with a novel ripple carry adder. Using multipoint and Monte Carlo analysis in the ADEXL design suite to ensure the reliability of all circuits using the Cadence Virtuoso with the GPDK45 nm technology. The proposed method is an alternative to high-speed electronic systems with potential benefits.

Design and analysis of hybrid 10T adder for low power applications

Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications. This study presents a novel architectural design for a 1-bit adder that utilizes 10 transistors. The concept relies on an energy-efficient hybrid logic multiplexer approach incorporating Gate Diffusion Input (GDI) logic. The primary goal of the suggested design for a hybrid full adder is to decrease power consumption while concurrently decreasing the required area. The suggested innovative architectural design for a full adder incorporates level restoration carry logic and ensures a complete swing output voltage. The designs have been analyzed in a standard environment using 45-nm CMOS process technology, with various supply voltages utilized. The evaluation of the adder cells focuses on speed, power consumption, power-delay-product (PDP), and space efficiency compared to the existing full adders. The recommended full adder cells were subjected to comprehensive simulation tests utilizing the Mentor Graphics environment. The results suggest that these cells surpass their counterparts, exhibiting a minimum of 80 % enhancements in their power-delay product (PDP) parameters. Also the comparisons have been made between the proposed full adders with and without level restoration techniques. The proposed level restoration technique based full adder yields better performance in terms of power and delay when compared to proposed full adder without level restoration.

English Translation Stylistic Features and Syntax Translation with Application of Knowledge Mapping

Abstract Aiming at the problems of excessive instantiation complexity, poor interpretability and low generalization ability of knowledge reasoning techniques, this paper unites inductive logic programming ILP with HET neural network to construct a hybrid logic rule and neural network knowledge graph reasoning model - HETIL model. The ILP is utilized to quantify the first-order logic rules, and the multi-layer rule space is constructed by arranging and combining the rules through logic symbols. The rules are instantiated and fed into the HET network, and the attention coefficients aggregate the node features to complete the end-to-end training and generate the rule learning model. Finally, the validity of the model is verified by machine translation experiments, and the results show that the accuracy of the HETIL model in syntactic structure types is more than 0.8 overall. The accuracy in terms of phrase structure reaches 0.879. The average BLEU value of the HETIL model can reach 29.24, which is 1.51 BLEU points higher than the benchmark model. Therefore, the effect of English translation by applying a knowledge graph is better than traditional machine translation.