Hump Effect Research Articles

Bilateral sidewall engineering Si1–x Ge x iTFET for low power display application * *This work was supported in part by the Ministry of Science and Technology of Taiwan, R.O.C., under Contact MOST109–2221-E-110–018-MY3.

In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve the I ON, resulting in a lower subthreshold swing average (S.S avg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that the S.S avg is improved to 21.5 mV dec−1 with an I ON/I OFF ratio of 106 at V D = 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec−1 has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.

Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

In this study, the degradation of the subthreshold swing (S.S.) and the hump effect are observed in the local oxidation of silicon (LOCOS) metal-oxide-semiconductor field-effect transistors (MOSFETs) under short-and long-term positive bias temperature instability tests, respectively. S.S. collapse is considered to be caused by anode hot-hole injection, and the hump effect occurs because the geometric structure from LOCOS isolation forms parasitic transistors on both sides of the channel, which can be verified by a Silvaco Technology computer-aided design (TCAD) simulation. In addition, the body effect measurement method is proposed to elucidate the mechanism of the hump effect for further confirmation of hump formation.

P‐1.4: Analysis of the Hump Characteristics in Poly‐Si Thin Film Transistor & Process a method to suppress hump effect

In this study, we investigate the transfer characteristics of low‐temperature polycrystalline silicon(LTPS) thin film transistors(TFTs) often show a “hump” in subthreshold region. This effect can be attributed to the presence of an enhanced electrical field at edges of the active layer. To reduce the hump effect which is one of the critical issues in ploy‐Si TFT, we focus on crowding of gate fringing field at channel edge and suggest a modified structure of channel edge. Using dry etching process, change the polysilicon layer at the edge of the channel from a steep profile to a slightly flat profile. And we confirmed that the severity of the hump effect is directly related to the edge profile of the polysilicon.

Suppressing Drain-Induced Barrier Lowering and Kink Effect in Low-Temperature Poly-Si TFTs Using a Partitioned Light Shield

Anomalous drain-induced barrier lowering (DIBL) is observed in n-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a full light shield (LS) structure. Drain current versus gate voltage curves exhibit a threshold voltage (V_TH) shift and hump effect as the drain bias increases, and demonstrate the unsaturated output property. Because of the inherent grain boundary and grain protrusion of LTPS TFTs, considerable impact ionization occurs, thus generating electron–hole pairs when operated at high current, leading to a floating body effect, that confers the occurrence of the kink effect. However, the unsaturated current characteristic is induced by the LS because of its coupling potential of the LS. Therefore, partitioned LS structures are proposed to further improve the DIBL and weak the kink effect.

Novel channel edge doping for hump reduction in LTPS TFTs

We proposed a new channel edge doping (CED) technique for hump reduction in n-type low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and validated it through experiments and technology computer-aided design (TCAD) simulations. The TCAD simulations indicate that the hump effect in LTPS TFTs is due to the high electron (e−) concentration (∼1016 cm−3) induced by an enhanced electric field (e-field) at the channel edge region along the width direction. In order to reduce the hump effect, we focused on decreasing the e− concentration at the channel edge. The CED process led to the selective control of the e− concentration at the channel edge. The decrease in the maximum e− concentration from 3.4 × 1016 to 2.9 × 1014 cm−3 at the channel edge using CED led to an effective reduction in the hump characteristic of LTPS TFTs. Furthermore, the CED process does not require any additional masks and is highly effective in hump reduction, rendering it beneficial for manufacturing active-matrix organic light-emitting diode displays.

AC stress reliability study on a novel vertical MOS transistor for non-volatile memory technology

This paper presents a novel high voltage vertical trench MOS transistor designed to be used in a Non-Volatile Memory (NVM) technology. Huge hump effect is demonstrated explaining some phenomenon observed during the AC stress. Quasi-static measurements are also reported showing that this vertical trench MOS transistor can be suitable for the use in an NVM environment. Finally, the AC stress reliability results demonstrate significant instabilities of both parasitic and main transistors. The comprehension is supported by TCAD simulations.

Performance enhancement and mechanism exploration of all-carbon-nanotube memory with hydroxylation and dehydration through supercritical carbon dioxide

Carbon nanotubes based non-volatile memories (NVMs) with excellent electronic properties can provide high bit density and energy efficiency. But with the limit of the process conditions, obtaining steep flanks with large hysteresis is still a challenge, while it is the prerequisite for stable program/erase/read operations. Herein, we adopt a novel treatment of supercritical CO2 (SCCO2) fluids to improve the performance of all-carbon-nanotube thin-film transistor (A-CNT-TFT) memory elements. By the treatment, the transfer characteristics of the A-CNT-TFTs achieve a 13.20 V hysteresis window, which is larger than 50% of the whole sweeping-voltage range. The disappearance of hump effect greatly improves the switching characteristics. The material analysis confirms that the SCCO2 fluids can reduce the defects in dielectric layer sufficiently and strengthen the connection between channel and gate dielectric. Furthermore, it is proposed that existence of hydroxyl groups in the carbon nanotubes contributes dominantly to the mechanism for charge storage, and the SCCO2 treatment enhances the charge storage by increasing the number of the hydroxyl groups. The work shows that the low-temperature SCCO2 treatment can better improve the performance of A-CNT-TFTs, which provides a promising option for nonvolatile charge storage memory devices.

Observation of trap-related phenomena in electrical performance of back-gated MoS2 field-effect transistors

Trap-related phenomena in the electrical performance of back-gated mechanical exfoliated MoS2 field-effect transistors are investigated in terms of the super linear increase in the drain current under positive gate bias and the shift of transfer curves with gate voltage stress. The super linear increase in drain current is only observed for the MoS2 field-effect transistors in the electron accumulation regime under positive gate bias, which can be attributed to a trap-assisted tunneling effect with S vacancies at the contact interface between metal Ti and MoS2. After thermal annealing of the devices in vacuum at 300 °C for 2 h, the almost complete metallization of Ti contacting with the MoS2 layer leads to the variation of the drain current relationship with drain voltage from a super linear to a linear increase, thus screening the efficacy of the mechanism of defect level assisted electron tunneling. The shift of transfer curves with gate voltage stress (denoted as hysteresis) is attributed to the defects near the interface between MoS2 and SiO2, which is slightly impacted by thermal annealing. The hump effect caused by parasitic transistors is also observed in back-gated mechanical exfoliated MoS2 field-effect transistors. These results further enrich the knowledge of the complex electrical characteristics of MoS2 field-effect transistors.

An analytical method for determining the optimum number of blades of the compound impeller in a low specific speed centrifugal pump

Reasonable methods for determining the optimum number of blades in a low specific speed centrifugal pump with closed-type impeller with splitters, i.e. compound impeller have been rather rare in the literature so far. In the article, a new analytical method was put forward to determine such an optimum number of blades by including the effect of turbulent boundary layer over impeller blades. Three conventional impellers with different numbers of full-length blades and two compound impellers with different numbers of splitters were designed and manufactured. The corresponding performance tests were then conducted. Results showed that the optimum numbers of blades exist for two kinds of impeller in terms of head at design point, pump efficiencies at design point and best efficiency point, and slope of head-flow rate curve at shut-off point. The estimated optimum numbers of blades are in good agreement with the numbers based on the experiments. The conventional impellers with full-length blades are more prone to the hump phenomenon than the compound impellers at the optimum numbers of blades. For the compound impellers, however, the hump effect is negligible at the optimum number of blades, and their head and efficiency are higher than those for the impellers with full-length blades. The method is applicable to compound impeller design in low specific speed centrifugal pumps.

Abnormal Hump Effect Induced by Hydrogen Diffusion During Self-Heating Stress in Top-Gate Amorphous InGaZnO TFTs

The mechanism of hydrogen-diffusion-induced electrical degradation under the self-heating effect for a top-gate amorphous InGaZnO (a-IGZO) thin-film transistor is examined in this article. Joule heating occurs in channels under high operating currents. The hydrogen in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{n}^{+}$ </tex-math></inline-formula> a-IGZO source/drain then diffuses into the channel and shifts the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {TH}}}$ </tex-math></inline-formula> ) in the negative direction. As the thermal conductivity of a-IGZO is lower than that of the surrounding insulator, the heat is preferentially dissipated from the sides of the channel. However, the heat in the center of the channel cannot by dissipated quickly. In addition, the unequal channel thermal effect induces a hump effect in the electrical characteristics, which is observed in COMSOL simulations. Hydrogen diffusion under self-heating stress (SHS) operation increases both the effective channel length and parasitic capacitance. The capacitance measurement method is used to clarify the mechanisms of these abnormal phenomena. Finally, the Joule heating effect is eliminated in a low-temperature environment at 200 K with a constant current, confirming that the degradation is indeed caused by the Joule heating effect.

Rigorous Study on Hump Phenomena in Surrounding Channel Nanowire (SCNW) Tunnel Field-Effect Transistor (TFET)

In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation. The SCNW TFET features an ultra-thin tunnel layer at source sidewall and shows a high on-current (ION). In spite of the high electrical performance, the SCNW TFET suffers from hump effect which deteriorates subthreshold swing (S). In order to solve the issue, an origin of hump effect is analyzed firstly. Based on the simulation, the transfer curve in SCNW TFET is decoupled into vertical- and lateral-BTBTs. In addition, the lateral-BTBT causes the hump effect due to low turn-on voltage (VON) and low ION. Therefore, the device design parameter is optimized to suppress the hump effect by adjusting thickness of the ultra-thin tunnel layer. Finally, we compared the electrical properties of the planar, nanowire and SCNW TFET. As a result, the optimized SCNW TFET shows better electrical performance compared with other TFETs.

Investigation of the anomalous hump phenomenon in amorphous InGaZnO thin-film transistors

In this work, we investigated an anomalous hump in the bottom-gate amorphous-InGaZnO thin-film transistors. The hump in the subthreshold region appeared at elevated temperature and disappeared after N2 atmosphere annealing. The anomalous hump phenomenon is attributed to the existence of both main current path composed by electron and parasitic current path induced by positive charges formed by adsorbed H2O molecules. With the increase of the testing temperature, the hump effect becomes significant since the formation of positive charges is strengthened by heat. This hump can be weakened by negative bias temperature instability stress at high temperature due to the charge-trapping mechanism.

High‐Performance Back‐Channel‐Etched Thin‐Film Transistors with an InGaO/InZnO Stacked Channel

Back‐channel‐etched (BCE) thin‐film transistors (TFTs) with an InGaO/InZnO stacked channel are developed, in which the InGaO and InZnO provide a highly acid‐resistant back channel and a high‐mobility front channel, respectively. The electrical performance of the TFT is optimized by adjusting the InGaO thickness. The best performance is achieved for the TFT with 10 nm thick InGaO. A thinner InGaO layer leads to inferior performance due to damage during the back‐channel‐etching process, while a thicker InGaO layer results in a hump effect and significant negative shifts in the threshold voltage (Vth) and turn‐on voltage (Von), which should be ascribed to the large total carrier number in the channel. The optimal TFT exhibits a high saturated field‐effect mobility of 28.9 cm2 V−1 s−1, a near‐zero Vth of −0.17 V, a Von of −0.49 V, a low subthreshold swing of 0.12 V dec−1, a high on‐to‐off current ratio of 3.5 × 109, and a low contact resistance between the source/drain (S/D) electrodes and channel. The TFT also exhibits high stability under bias thermal stress.

Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios

The hetero-gate dielectric (HGD) structure was recently experimentally demonstrated to enhance the electrical performance of tunnel field-effect transistors (TFETs). This study examined the mechanisms underlying the HGD structure functioning and investigated the design of the structure to enhance the electrical characteristics of TFETs with different ratios of low- and high-k equivalent oxide thicknesses (EOT). The on-current enhancement by the source-side dielectric heterojunction, which directly modulates the on-state tunnel width, was much larger than that by the drain-side dielectric heterojunction, which indirectly affects the on-current by modulating the subthreshold tunnel width. The subthreshold swing is improved by the formation of a conduction band well near the source-channel junction. However, the swing improvement is limited by the hump effect when this local potential well approaches the source. The optimal design of the HGD structure and the maximal enhancement of on-current considerably depend on the EOT ratio of low- and high-k dielectrics. The on-current is most enhanced by the optimized HGD structure at a low/high-k EOT ratio of ten times, that is, approximately 160% of the on-current of the uniform high-k TFET counterpart. Due to the continuous trend of increasing the k-values or scaling EOTs, understanding the dependence of device physics and design on the low/high-k EOT ratio is crucial to optimize the performance of HGD-TFETs.

Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors

This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.

Abnormal ${C}$ –${V}$ Hump Effect Induced by Hot Carriers in Gate Length-Dependent p-Type LTPS TFTs

We investigate the abnormal current-voltage (C-V) hump effect of p-type low-temperature polysilicon (LTPS) thin-film transistors (TFTs) which have undergone high current operations. Experimental results indicate localized electron trapping in the gate insulator (GI), which is carried out near the drain. The ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) enhancement is due to the reduction of effective length, and the OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) decrease as the electron tunneling path distance increases. These can be observed after hot carrier stress in current characteristics. The C-V measurements demonstrate that the threshold voltage ( ${V}_{\text {th}}$ ) shift is associated with the gate length. In addition, capacitance-voltage measurements also show that this localized trapping region remains the same in length, regardless of channel length. Hence, a model is proposed to explain how the electric field, which is gate length-dependent, affects the source side of the device, and then lowers the source barrier height. This leads to bulk leakage, which causes the subthreshold swing degradation at device scale down.

A Novel Heat Dissipation Structure for Inhibiting Hydrogen Diffusion in Top-Gate a-InGaZnO TFTs

In order to better understand the reliability issues in top-gate a-InGaZnO (a-IGZO) thin-film transistors, this letter investigates the degradation mechanism of a device under self-heating stress (SHS). After applying hot carrier stress, a negative threshold voltage ( ${V} _{\text {TH}}$ ) shift, a hump effect, and normally- ON current degradation were found. COMSOL simulation results of hydrogen diffusion in the source and drain (n+ region) of a-IGZO show that Joule heat was generated in the channel during SHS, which leads to hydrogen diffusion in the central and side channels. The unequal channel thermal effect results in a hump effect in the electrical characteristics, and the self-heating effect becomes more prominent as the channel width increases. To minimize the effects of these abnormal phenomena under high current operation in future display applications, a method of creating structural divisions in the channel width is used to aid overall heat dissipation and reduce the effect of SHS degradation.

Investigation of Hump Effect of Amorphous In-Ga-Zn-O Thin-Film Transistor Using Scanning Capacitance Microscopy

We investigated the hump effect, which is induced by positive gate-bias stress, of an amorphous In-Ga-Zn-O thin-film transistor with the self-aligned top-gate structure. By applying scanning capacitance microscopy to the transistor with the hump effect, we directly detected a partial increase of carrier density at the channel edges in the channel width direction. The width of the high-carrier-density regions was approximately ${1}\,{\mu \text {m}}$ at each side edge, which is consistent with the estimation by electrical measurements. Such high-carrier regions at the channel edges can act as parasitic transistors with a more negative threshold voltage, generating the hump in the transfer characteristics. Our results support the idea that the hump effect is derived from the parasitic transistors at the channel edges directly and show that the scanning capacitance microscopy provides complementary information to the electrical measurements and is an effective tool to evaluate the hump effect.

Review—Technology Trends of Poly-Si TFTs from the Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing low-temperature polycrystalline-Si (LTPS) are critical for system-on-panel applications. The requirements for LTPS are a high quality, a large grain size and position control of the nucleation. Many promising crystallization methods have been developed to satisfy these requirements. Herein, two scientific discoveries related to the low-temperature crystallization and high-performance TFT structure using the tunnel effect are introduced. Hydrogens in an amorphous (a-Si) film greatly accelerate the crystal velocity and improved the crystallinity of the excimer-laser annealing (ELA) poly-Si film, thereby providing a high-quality, a large-grained film referred to as secondary-grain film, under the solid-phase condition. In addition, a soft X-ray crystallization (SXC) method was developed. It reduces the threshold temperature of crystallization for a-Si, SiXGe1-X and Ge films by 100°C–140°C in comparison to that for films prepared by conventional thermal crystallization. The SXC method is expected to become the critical low-temperature crystallization method in the era of the flexible electronics. On the other hand, although high-performance TFTs that utilize large single-crystalline grains have been intensively researched, such research has not been successful from the viewpoint of mass production. A novel device structure – tunneling dielectric TFT (TDTFT)–has been developed. The TDTFT reduces the gate-off current to less than 1/10 of that with a conventional TFT. In addition, the TDTFT improved the hump effect. We conclude that the triple-gate (Fin) TDTFT will be a promising candidate for next-generation poly-Si TFT structures.

Parametric study and surface morphology analysis of electron beam selective melting

PurposeThis paper aims to study the effect of processing parameters and the fundamental mechanism of surface morphologies during electron beam selective melting.Design/methodology/approachFrom the powder-scale level, first, the discrete element method is used to obtain the powder bed distribution that is comparable with the practical condition; then, the finite volume method is used to simulate the particle melting and flowing process. A physically reliable energy distribution of the electron beam is applied and the volume of fluid method is coupled to capture the free boundary flow. Twelve sets of parameters grouped into three categories are examined, focusing on the effect of scan speed, input powder and energy density.FindingsAccording to the results, both melting pool width and depth have a positive relation with the energy density, whereas the melting pool length is insensitive to the scan velocity change. The balling effect is attributed to either an insufficient energy input or the flow instability; the hump effect originates from the mismatch between electron beam moving and the fluid flow. The scan speed is a key parameter closely related to melting pool size and surface morphologies.Originality/valueThrough a number of case studies, this paper gives a comprehensive insight of the parameter effects and mechanisms of different surface morphologies, which helps to better control the manufacturing quality of electron beam selective melting.