Huffman Decoding Research Articles

Comment on “Efficient Huffman decoding” and “An efficient finite-state machine implementation of Huffman decoders”

Comment on “Efficient Huffman decoding” and “An efficient finite-state machine implementation of Huffman decoders”

Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit

A study of the MPEG-2 video decoding standard in Main Profile @ Main Level has been performed, comparing the different solutions existing for the VLSI implementation of the basic functions (Huffman decoding, IDCT...) included in the standard. Afterwards, a new dynamically configurable architecture is proposed for the memory manager, which is necessary to deal with the large data flow inside the decoder. It is aimed at interfacing the external memory, arbitrating the access requests coming from the different decoding units and allowing generic memory requests through the definition of virtual addresses. It is shown that, by means of a particular data organization, the circuit requires an external memory, which is a 2-MB DRAM in fast page or EDO mode, accessible via a 64-bit bus. The memory manager works at 27 MHz and allows a real-time decoding for MP @ ML bitstreams. It has been synthesized in a 0.8-μm two-metal CMOS technology and presents a total area of 5.4 mm2 for 6500 gates.

Single Chip Dual---Issue RISC Processor for Real---Time MPEG---2 Software Decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.

Low power parallel Huffman decoding

A low power design technique for a parallel Huffman decoder is presented. According to the length of the incoming Huffman codeword, the proposed strategy makes the barrel shifter in the parallel Huffman decoder turn off the unnecessary shifting bits to reduce power dissipation. The result of a SPICE simulation indicates that up to 50 percent power reduction in the barrel shifter may be achieved with the proposed technique.

A parallel decoder of programmable Huffman codes

Huffman coding, a variable-length entropy coding scheme, is an integral component of international standards on image and video compression including high-definition television (HDTV). The high-bandwidth HDTV systems of data rate in excess of 100 Mpixels/s presents a challenge for designing a fast and economic circuit for intrinsically sequential Huffman decoding operations. This paper presents an algorithm and a circuit implementation for parallel decoding of programmable Huffman codes by using the numerical properties of Huffman codes. The 1.2 /spl mu/m CMOS implementation for a single JPEG AC table of 256 codewords of up to 16-b codeword lengths is estimated to run at 10 MHz with a chip area of 11 mm/sup 2/, decoding one codeword per cycle. The design can be pipelined to deliver a throughput of 80 MHz for decoding input streams of consecutive Huffman codes. Furthermore, our programmable scheme can be easily integrated into data paths of video processors to support different Huffman tables used in image/video applications. >

Algorithmic and architectural enhancements for real-time MPEG-1 decoding on a general purpose RISC workstation

Traditional video decoders require use of specially designed video decompression processors. We present novel algorithmic and architectural enhancements that allowed for the first time the real-time decompression of MPEG-1 video and audio streams on a low-end, general purpose RISC processor. For video decompression, efficient algorithmic implementations were derived by examining the Huffman decoder, the inverse quantizer and the inverse DCT as a single system. For audio decompression, a new DCT based implementation of the subband filtering operation yields 30% speed improvement in the audio decoding process and 17% speed improvement in overall audio and video decoding. Besides algorithmic enhancements, a new set of multimedia instructions and minor changes in the design of a traditional RISC ALU allowed increased parallelism of pixel-based operations with minimal design and control overhead. Experimental results show that with the synergistic combination of algorithmic and architectural enhancements a multimedia-enhanced RISC processor can achieve higher decoding rates than generic RISC and CISC processors, even when these processors operate at higher clock rates and have larger instruction and data caches. >

High speed pattern matching for a fast Huffman decoder

The fast Huffman decoding algorithm has been used in JPEG, MPEG and image data compression standards, etc. And code compression is a key element in high speed digital data transport. A major compression is performed by converting the fixed-length codes to variable-length codes through an entropy coding scheme. Huffman coding combined with run-length coding is shown to be a very efficient coding scheme. To speed up the process of search for a symbol in a Huffman tree and to reduce the memory size we have proposed a tree clustering and a pattern matching algorithm to avoid high sparsity of the tree. The method is shown to be very efficient in memory size and fast searching for the symbol. For an experimental video data with Huffman codes extended up to 16 bits in length, i.e. it is used for the standard JPEG, the result of experiments show that the proposed algorithm has a very high speed and performance. The design of the decoder is carried out using silicon-gate CMOS process. >

Efficient decoding of compressed data

In this article, we discuss the problem of enhancing the speed of Huffman decoding. One viable solution to this problem is the multibit scheme which uses the concept of k-bit trees to decode up to k bits at a time. A linear-time optimal solution for the mapping of 2-bit trees into memory is presented. The optimal solution is derived by formulating the memory mapping problem as a binary string mapping problem and observing that at most four different 4-bit patterns can occur within any 2-bit Huffman tree. In addition to reducing the processing time of decoding, the optimal scheme is storage efficient, does not require changes to the encoding process, and is suitable for hardware implementations

Design and hardware implementation of a memory efficient Huffman decoding

Hardware design of a high speed and memory efficient Huffman decoder, introduced in Hashemian (1993) is presented. The algorithm developed is based on a specific Huffman tree structure using a code-bit clustering scheme. The method is shown to be extremely efficient in the memory requirement, and fast in searching for the desired symbols. For experimental video data with code-words extended up to 13 bits, the entire memory space needed is shown to be 122 words in size, compared with normally 2/sup 13/=8196 words memory space requirement. The design of the decoder is carried out using the Si-gate CMOS process. >

High-speed VLSI architectures for Huffman and Viterbi decoders

Pipelined and parallel architectures for high-speed implementation of Huffman and Viterbi decoders (both of which belong to the class of tree-based decoders) are presented. Huffman decoders are used for lossless compression. The Viterbi decoder is commonly used in communications systems. The achievable speed in these decoders is inherently limited due to the sequential nature of their computation. This speed limitation is overcome using a previously proposed technique of look-ahead computation. The incremental computation technique is used to obtain efficient parallel (or block) implementations. The decomposition technique is exploited to reduce the hardware complexity in pipelined Viterbi decoders, but not in Huffman decoders. Logic minimization is used to reduce the hardware overhead complexity in pipelined Huffman decoders.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Combined Huffman and convolutional codes: concatenated form without feedback

In this letter, a new scheme for joint source and channel coding is introduced in which both Huffman coding and convolutional coding are used in concatenated form. This is a reduction in overall complexity, in comparison with a hard decision decoder followed by a Huffman decoder.