Hsiao Code Research Articles

Hsiao Codes Properties in Discrete Devices Technical Diagnostics Systems

The error detection features by modified Hamming codes — codes with odd column weights, or Hsiao codes — are analyzed. The error detection properties of Hsiao codes are considered separately for data symbols, as well as for all code word symbols. It is shown that Hsiao codes detect any errors with odd multiplicities and errors with multiplicities d < 4. The Hsiao codes error detection performance is compared with the error detection performance by classic Hamming codes. The experiments results showing the Hsiao codes high efficiency in organizing the calculation testing at the automation device outputs are given. Hsiao codes can be very effectively used in solving problems of automation devices synthesis with the malfunctions and errors detection in calculations, including the devices synthesis with controllable structures and with concurrent calculation testing circuits.

Data Integrity Enhancement with Interleaved Hsiao Code and CRC Error Detection and Correction – A Brief Review

Data Integrity Enhancement with Interleaved Hsiao Code and CRC Error Detection and Correction – A Brief Review

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

Mitigating single event upset method for Zynq MPSoC

Single event upset (SEU) have direct influence on the reliability of Zynq Multi-Processor System-on-Chip (MPSoC). To mitigate SEU, the method based on the structural features of the two ARM cores in Zynq is proposed. Dual-core mutual detection and rollback recovery are utilized to detect and repair the errors caused by SEU. Hsiao code is also integrated to enhance the SEU-resistance of on-chip memory. Experimental results show that the proposed method can correct error of ARMs and on-chip memory error.

An Algorithm for the Computer Serarch of High Coded Rate Hsiao Code

An Algorithm for the Computer Serarch of High Coded Rate Hsiao Code

Error-correction coding in CMOS RAM resistant to the effect of single nuclear particles

Coders/decoders that are used in RAM to enhance the data storage reliability on exposure to single nuclear particles are analyzed. If the numbers of check bits are equal, a Hsiao decoder has a lower signal propagation delay than a decoder of the modified Hamming code. A decoder of the extended Hsiao code with additional check bits has the lowest delay among all decoders. When Hsiao decoders with units with a truncated correction circuit, a symmetrically simplified circuit for error vector calculation, and a circuit forming the error signal without the use of the error vector are used in RAM, the critical path lengths and the occupied chip area may be reduced if the detection of triple errors is excluded. The equal efficiency of Richter decoders and coders/decoders obtained through optimization based on genetic algorithms is substantiated for SEC-DAEC codes.

다양한 유전 연산자를 이용한 저전력 오류 정정 코드 설계

The memory is very sensitive to the soft error because the integration of the memory increases under low power environment. Error correcting codes (ECCs) are commonly used to protect against the soft errors. This paper proposes a new genetic ECC design method which reduces power consumption. Power is minimized using the degrees of freedom in selecting the parity check matrix of the ECCs. Therefore, the genetic algorithm which has the novel genetic operators tailored for this formulation is employed to solve the non-linear power optimization problem. Experiments are performed with Hamming code and Hsiao code to illustrate the performance of the proposed method.

다목적 Error Correcting Code의 새로운 설계방법

Error correcting codes (ECCs) are commonly used to protect against the soft errors. Single error correcting and double error detecting (SEC-DED) codes are generally used for this purpose. The proposed approach in this paper selectively reduced power consumption, delay, and area in single-error correcting, double error-detecting checker circuits that perform memory error correction. The multi-objective genetic algorithm is employed to solve the non -linear optimization problem. The proposed method allows that user can choose one of different non-dominated solutions depending on which consideration is important among them. Because we use multi-objective genetic algorithm, we can find various dominated solutions. Therefore, we can choose the ECC according to the important factor of the power, delay and area. The method is applied to odd-column weight Hsiao code which is well- known ECC code and experiments were performed to show the performance of the proposed method.

Reducing Power in Error Correcting Code using Genetic Algorithm

Abstract — This paper proposes a method which reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory error correction code. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting codes. The genetic algorithm is employed to solve the non linear power optimization problem. The method is applied to two commonly used SEC-DED codes: standard Hamming and odd column weight Hsiao codes. Experiments were performed to show the performance of the proposed method. Keywords — Error correcting codes, genetic algorithm, non-linear power optimization, Hamming code, Hsiao code.I. I NTRODUCTION S technology continues to scal e with smaller features sizes, lower power supply voltages, and higher operating frequencies, the soft error rate in logic circuits is rapidly increasing. Concurrent error detection using error correcting codes (ECCs) at the outputs of a circuit provides means to detect soft errors quickly before they have a chance to propagate and compromise the data integrity of a system. Error correcting codes are commonly used to protect against soft errors and thereby enhance system reliability and data integrity [1]. Single error correcting and double error detecting (SEC-DED) codes are generally used for this purpose. These codes are able to correct single-bit errors and detect double-bit errors in a codeword. A design criterion that has become very important in recent times is power reduction. With increasing miniaturization of devices, power has become a first-order design consideration motivating researchers to look at techniques of reducing power consumption in all components of system design. For memory ECC, power reduction is also an important consideration, since the ECC checker circuit is activated during reading and writing access to the memory. As power has become an important consideration, researchers have begun looking at methods to reduce power consumption in error detection circuitry [2-4].

Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits

The approach proposed in this paper reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory ECC. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting code. The non-linear power optimization problem is solved using two methods, genetic algorithms and simulated annealing. Both the methods are applied to two SEC-DED codes: standard Hamming codes and odd-column-weight Hsiao codes. Experiments on actual memory traces of Spec and MediaBench benchmarks indicate that considering power along with area and delay when selecting the parity check matrix can result in power reductions of up to 27% for Hsiao codes and up to 41% for Hamming codes. Experiments are also performed to motivate the choice of parameters of the non-linear optimization algorithms, using sensitivity analysis of the low-power solutions to the choice of the different parameters of each algorithm.

Single error correcting and double error detecting coding scheme

A new coding technique for single error correction and double error detection in computer memory systems is proposed. The number of 1s in the parity check matrix for the proposed coding is fewer than all currently available codes for this purpose, except in two cases when they are almost equal to that obtained by Hsiao code. This results in simplified encoding and decoding circuitry for error detection and correction.