Hot-carrier Stress Degradation Research Articles

Implication of Self-Heating Effect on Device Reliability Characterization of Multi-Finger n-MOSFETs on 22FDSOI

In this paper, the self-heating effect for multi-finger fully depleted SOI nMOSFETs is investigated. The layout parameters of the transistor are varied, and the conductance-based method is used for the extraction of the thermal resistance. An empirical-based scalable thermal resistance model that accounts for geometrical layout parameters is developed. Further, hot carrier stress degradation is examined, and a correlation between self-heating and hot carrier degradation is established. The associated self-heating with geometrical dimension influences the amount of hot carrier degradation and should be taken into account for accurate degradation modeling. It is found that with the increase of temperature, the contribution of the parasitic bias temperature instability effect increases the drift of the threshold voltage. Improved thermal and reliability performance is achieved for the device structures where a continuous active area is divided into multiple smaller active regions.

The Relationship Between Resistive Protective Oxide (RPO) and Hot Carrier Stress (HCS) Degradation in n-Channel LD SOI MOSFET

This article investigates the influence of resistive protective oxide (RPO) layer density and hot carrier stress (HCS) degradation in n-channel lateral diffused silicon-on-insulator metal–oxide–semiconductor field-effect transistors. At the beginning of HCS at a higher gate voltage ( ${V}_{G}$ ), the threshold voltage shifts and subthreshold swing increase, but the ON-state current will still increase abnormally. The drain current and drain voltage ( ${I}_{D}$ – ${V}_{D}$ ) transfer curves indicate that channel resistance or drift region resistance dominates degradation between low- ${V}_{G}$ and high- ${V}_{G}$ respectively. It also found different degradation behavior by extracting the resistances at low- ${V}_{G}$ and high- ${V}_{G}$ to stress time. In addition, technology computer-aided design (TCAD) software results show maximum impact ionization of high- ${V}_{G}$ , in which the direction of the electric field is toward RPO, resulting in the injection of holes into RPO during HCS. Finally, the simulated drain current and gate overdrive voltage curves for numerous interface states and numerous oxide traps show that the abnormal ${I}_{ \mathrm{\scriptscriptstyle ON}}$ enhancement is due to the hole trapping in the RPO and the degradation is closely related to the different density of RPO. In this article, we determine the mechanism of HCS degradation and propose methods to optimize high-voltage (HV) device performance and reliability.

TCAD simulation of hot-carrier stress degradation in split-gate n-channel STI-LDMOS transistors

A combined experimental and simulation analysis of the degradation mechanisms induced by hot carriers in a silicon-based split-gate n-channel LDMOS transistor featuring an STI structure is reported. In this regime, electrons can gain sufficient kinetic energy necessary to create charged traps at the silicon/oxide interface, thus inducing device degradation and causing the shift of the electrical parameters of the device. In particular, the on-resistance degradation in linear regime has been experimentally characterized at different stress conditions and at room temperature. The hot-carrier degradation has been reproduced in the frame of TCAD simulations by using physical-based models aimed at reproducing the degradation kinetics. An investigation of the electron distribution function at different stress conditions and its dependence on the split-gate bias is carried out achieving a quantitative understanding of the role played by hot electrons in the hot-carrier degradation mechanisms of the device under test.

Abnormal Relationship Between Hot Carrier Stress Degradation and Body Current in High-k Metal Gate in the 14-nm Node

This letter discusses the hot carrier stress (HCS) degradation mechanisms for different gate voltages ( $\text{V}_{\textsf {G}}$ ) in FinFET devices, and finds the abnormal relationship between HCS degradation and body current under high $\text{V}_{\textsf {G}}$ . According to the distributions of lifetime ( ${\tau }$ )- $\text{I}_{\textsf {B}}$ and ${\tau }$ -drain current ( $\text{I}_{\textsf {D}}$ ), it is found that the ${\tau }$ under the high $\text{V}_{\textsf {G}}$ is related to the $\text{I}_{\textsf {D}}$ instead of the $\text{I}_{\textsf {B}}$ . In addition, as the $\text{V}_{\textsf {G}}$ increases from low to middle to high values, the HCS degradation mechanism exhibits single vibrational excitation, electron-electron scattering, and multiple vibrational excitation (MVE) models, respectively. Therefore, the HCS degradation mechanism at higher $\text{V}_{\textsf {G}}$ is not dominated by the traditional impact ionization but by the carrier concentration of the channel. Finally, according to the results of fitting MVE model, the reason for breaking the Si-H bonds to form dangling bonds is the bending vibrational mode.

Physics-Based Analytical Model for HCS Degradation in STI-LDMOS Transistors

A physics-based analytical model for the on-resistance in the linear transport regime and its application as an alternative tool for the investigation of the hot-carrier stress degradation in shallow-trench-isolation-based laterally diffused MOS devices are presented. The extraction of the model and its validation by comparison with experimental and TCAD data are reported. A thorough investigation of the degradation under low- and high-gate stress biases, corresponding to saturation and impact-ionization regimes, is carried out to gain an insight on the overall bias and temperature dependences of the parameter drifts.

Hot-carrier stress induced degradation in Multi-STI-Finger LDMOS: An experimental and numerical insight

Degradation induced by hot-carrier stress (HCS) in a Multi-STI-Finger (MF) LDMOS is analyzed through both electrical measurements and TCAD simulations. The critical HCS issues have been first addressed on a conventional STI-based LDMOS. Then, the detrimental effect of extended Si/SiO2 interfaces along the silicon fingers in the MF-LDMOS has been widely investigated with particular focus on its dependence on biases, ambient temperature, and layout variations. Experimental results are analyzed and discussed on the basis of numerical simulations. The application of a time-dependent HCS degradation model is successfully proved for the first time on the conventional and MF-LDMOS devices at different stress biases and ambient temperatures.

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.