Hot-carrier Stress Conditions Research Articles

Investigation Between Recover Behavior and Defect With Variation of Light Source in AlGaN/GaN HEMTs After Hot-Carrier Stress

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">In this paper, a light recovery method is proposed to analyze defect concentration and energy level distribution by changing the wavelength. The AlGaN/GaN high electron mobility transistors (HEMTs) under hot carrier stress (HCS) conditions will experience a severe electrical degradation. The threshold voltage (V_th) shifts to the right, and the on current and the off current both decrease. TCAD simulations of the electric field distribution and energy bands are performed to examine the degradation behaviors under HCS on the GaN-based HEMTs. The degradation of electrical characteristics can be effectively recovered by using the illumination method in AlGaN/GaN HEMTs. In addition, the light wavelength of illumination is positively correlated with the recovery effect, which is expected to provide effective measurements and analyses for AlGaN/GaN HEMT devices, which is expected to clarify the defect energy level distribution of HEMT device degradation</i> .

Hot-carrier reliability and performance study of transistors with variable gate-to-drain/source overlap

Flexibility on the gate-to-drain/source overlap length is useful for selecting the best compromise between device performance (including short channel effects and gate scaling, ON-state current, parasitic overlap capacitance), and the device reliability to hot-carrier degradation. In this paper, the performance and reliability of transistors with variable overlap is studied in a 40 nm CMOS technology. A double-hump is observed in the substrate current characteristic in function of the gate voltage for low-overlap transistors. An analysis of the origin of the second substrate current hump is conducted, and it is attributed to impact ionization at the drain-side, source-side or both depending on the overlap. TCAD simulations are performed to explain the two possible origins of the double-hump characteristic, which are degradation of the gate control over the channel due to low overlap or hot-carrier trapping. Finally, electrical characterizations are conducted to measure the degradation rate for various overlap lengths. It is observed that a longer overlap gives the transistor a longer lifetime under hot-carrier stress conditions.

Analysis of abnormal threshold voltage shift induced by surface donor state in GaN HEMT on SiC substrate

This study investigates the recovery behavior of GaN high-electron mobility transistors on SiC substrates under different hot-carrier stress conditions. The threshold voltage shifts positively due to hot electron trapping at the buffer layer under hot-carrier stress. However, the recovery between semi-on (Vt &amp;lt; VG &amp;lt; 0 V) hot-carrier stress and on-state (VG &amp;gt; 0 V) carrier stress is significantly different. This phenomenon is systematically discussed in terms of the applied gate voltage under stress condition, which affects the occupation of the surface donor states. After applying a semi-on hot-carrier stress, the threshold voltage continues to shift positively after relaxing the applied voltage. In contrast, the threshold voltage exponentially recovers after applying an on-state hot-carrier stress. Silvaco technology computer aided design (TCAD) simulation was performed to verify the effect of the surface donor state on the threshold voltages. Since switching between on-state and off-state in RF-applications includes both conditions, we suggest that the surface donor states are crucial to determine the failure of devices.

Obtaining impact ionization-induced hole current by electrical measurements in gallium nitride metal–insulator–semiconductor high electron mobility transistors

In this paper, an extraction method for measuring impact ionization-induced hole current in gallium nitride (GaN) metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) is proposed. The results show that the non-monotonic impact ionization current characteristic can be easily acquired by the extraction method. Further, different hot-carrier stress (HCS) conditions can be obtained based on the I G–V G curve, and the reliability tests can act as verification of the impact-ionization curve. In addition, electrical reliability tests indicate that the threshold voltage (V TH) shift and on-state current (I on) degradation in the MIS-HEMTs have a positive correlation to impact ionization-generated hole current. During HCS operation, the V TH will shift positively and I on decreases due to hot electrons trapping into the GaN layer. This model is validated by TCAD simulation.

Crystallographic-orientation-dependent GIDL current in Tri-gate MOSFETs under hot carrier stress

The Gate-Induced-Drain-Leakage (GIDL) current in Tri-gate MOSFETs for different crystal orientations and fin widths under hot carrier stress was systematically examined by comparing the experiments and a theoretical GIDL current model. A band-to-band tunneling model was used to fit the measured GIDL current with different crystal orientations, fin widths and hot carrier stress conditions. The extracted values of model parameters provide a consistent explanation for the orientation dependence of GIDL current in Tri-gate MOSFETs. After hot carrier stress, the larger variation of a model parameter value in non-rotated device for strongly suggests a higher density of dangling bonds on (110) surfaces in Tri-gate MOSFETs. With considering hot carrier effects on the GIDL current and the drain current degradation, it is found that fin widths can be reduced further by fabricating multiple gate devices in rotated wafer.

Characterization and modeling of electrical stress degradation in STI-based integrated power devices

Lateral DMOS transistors are widely used in mixed-signal integrated-circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. In this review, the electrical characteristics of the STI-based LDMOS transistors are investigated over an extended range of operating conditions through experiments and numerical analysis. The LDMOS high electric-field characteristics are explained to the purpose of investigating the effects on reliability and device performance under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to provide an understanding of the degradation kinetics and mechanisms. TCAD simulations of the degradation are finally proposed to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.

Linear Drain Current Degradation of FG-pLEDMOS Transistor Under Pulse Gate Stress With Different Rising and Falling Edges

Linear drain current degradation of a field-gate p-channel lateral extended drain MOS (FG-pLEDMOS) transistor for different ac hot-carrier stress conditions has been experimentally investigated in this paper. It is noted that hot-carrier degradation strongly depends on the time of the rising and falling edges of the gate signal pulse. Faster rising and falling edges of the gate pulse will induce more serious hot-carrier degradation. Moreover, the experimental results reveal that the falling edges of the gate pulse show more distinct influence upon hot-carrier degradation than that of the rising edges. In this way, the pulse gate stress with fast falling edges should be considered for evaluating the hot-carrier-induced lifetime of a laterally diffused MOS working with fast gate signal pulse edges.

Examination of hot-carrier stress induced degradation on fin field-effect transistor

Degradation in fin field-effect transistor devices was investigated in detail under various hot-carrier stress conditions. The threshold voltage (VTH) shift, substrate current (IB), and subthreshold swing were extracted to determine the degradation of a device. The power-law time exponent of the VTH shift was largest at VG = 0.3 VD, indicating that the VTH shift was dominated by interface state generation. Although the strongest impact ionization occurred at VG = VD, the VTH shift was mainly caused by electron trapping resulting from a large gate leakage current.

The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors

An effect, called random trap fluctuation (RTF), is proposed to study the threshold voltage (Vth) fluctuation of metal oxide semiconductor field effect transistors (MOSFETs) under Fowler-Nordeim (FN) or hot carrier (HC) stress condition. Experiments have been demonstrated on n-channel MOSFETs, and it was found that not only the random dopant fluctuation (RDF) but also the stress-induced traps vary the Vth fluctuation. More importantly, the stress-induced trap barrier determines the Vth fluctuation. For devices after FN stress, Vth fluctuation is enhanced since the trap barrier regulates the transporting carriers. For devices after HC stress, Vth fluctuation is supressed since the carriers are backscattered into the channel by the trap barrier and fewer carriers with higher energy pass through the barrier. These results provide us a clear understanding on another source of Vth fluctuations in addition to the RDF as devices are further scaled.

Effect of electron–electron scattering at an elevated temperature on device lifetime of nanoscale nMOSFETs

The effect of electron–electron scattering (EES) on a nanoscale n-channel metal–oxide–semiconductor field-effect transistor was investigated. Experimental results indicate that EES stress creates more interface states and negative oxide charges than does channel hot-carrier (CHC) stress. Moreover, shifts of gate induced drain leakage current and substrate current confirm that defects generated by EES are distributed in the channel and drain region. Thus, the worst case hot carrier stress condition should be modified from CHC stress to EES stress.

Microscopic scale characterization and modeling of transistor degradation under HC stress

This paper presents a theoretical framework about interface states creation rate from SiH bond breaking at the Si/SiO2 interface during Hot Carrier (HC) stress. It involves two mains mechanisms of bond breaking through incident carriers, either being very energetic or very numerous but less energetic. This concept allows physical modeling of the reliability of MOS transistors, for different HC stress conditions. Simulation is validated by measurement of both defect lateral profiles and degradation of MOS parameters. This poses a general framework for the study of HC degradation at defect level.

Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal–Oxide–Semiconductor Field-Effect Transistors by a Novel Direct Current Current–Voltage Technique

Shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal–oxide–semiconductor (CMOS) process. A novel direct current current–voltage (DCIV) technique demonstrated with multiple sharp peak signals is proposed to characterize interface state generation in the channel and in the STI drift regions separately. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by proposed technique. A two-dimensional numerical device simulation is performed to obtain insight into the proposed technique and device degradation characteristics under hot-carrier stress conditions. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our results show that the maximum Isub stress becomes the worst hot-carrier degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

Dependence of Hot Carrier Reliability and Low Frequency Noise on Channel Stress in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, the dependence of low-frequency (LF) noise, such as 1/f noise and random telegraph signal (RTS) noise, and the hot carrier reliability in n-channel metal–oxide–semiconductor field-effect transistors (NMOSFETs) on channel stress has been studied. The normalized noise power spectral density (SID /ID2) and RTS amplitude of NMOSFETs with compressive channel stress are greater than those with tensile channel stress because the active traps contributing to RTS noise with compressive stress are distributed closer to the Si/SiO2 interface. LF noise characteristics, as well as device performance are enhanced by introducing tensile channel stress to nanoscale NMOSFETs. However, it is shown that device degradation caused by tensile channel stress is greater than that caused by compressive channel stress under channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) stress conditions. Therefore, concurrent consideration of reliability and LF noise characteristics as well as dc device performance is necessary in channel strain engineering for next generation complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) especially for analog or mixed signal integrated circuit applications.

Dependence of Hot Carrier Reliability and Low Frequency Noise on Channel Stress in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, the dependence of low-frequency (LF) noise, such as 1/f noise and random telegraph signal (RTS) noise, and the hot carrier reliability in n-channel metal–oxide–semiconductor field-effect transistors (NMOSFETs) on channel stress has been studied. The normalized noise power spectral density (SID/ID2) and RTS amplitude of NMOSFETs with compressive channel stress are greater than those with tensile channel stress because the active traps contributing to RTS noise with compressive stress are distributed closer to the Si/SiO2 interface. LF noise characteristics, as well as device performance are enhanced by introducing tensile channel stress to nanoscale NMOSFETs. However, it is shown that device degradation caused by tensile channel stress is greater than that caused by compressive channel stress under channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) stress conditions. Therefore, concurrent consideration of reliability and LF noise characteristics as well as dc device performance is necessary in channel strain engineering for next generation complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) especially for analog or mixed signal integrated circuit applications.

Electrical characterization of polycrystalline silicon thin film transistors crystallized by a new alignment sequential lateral solidification process

In the conventional sequential lateral solidification (SLS) method for polycrystalline silicon thin-film transistors (poly-Si TFTs), as a starting process in general, one just performs a basic pre-alignment of the substrate on the stage and applies laser irradiation for a whole substrate area scan. Therefore, each thin-film transistor (TFT) has different grain boundary (GB) locations in a corresponding channel region. The number of GBs in the channel also varies from one to two, which can give rise to electrically non-uniform TFT characteristics and an image quality deterioration of the panel. We developed a new alignment SLS method for controlling the GB location in the TFT channel region, allowing us to locate the GB at the same position in the channel region of each TFT. We fabricated TFT by applying the new alignment SLS process and compared the TFT electrical characteristics between a normal SLS method and the new one. We also analyzed degradation phenomena under hot carrier stress conditions for lightly doped drain n-type metal oxide semiconducting field effect transistors.

A Practical Model Assessing the Degradation of Polycrystalline Silicon TFTs Due to DC Electrical Stress

Degradation phenomena under the application of a variety of hot-carrier stress conditions were investigated in n-channel top-gate polysilicon thin-film transistors of various channel widths, fabricated by sequential lateral solidification excimer laser annealing. A simple and practical model was developed in order to predict the dc-stress-induced degradation and the evolution during stress of the critical electrical parameters of device performance, such as the threshold voltage. The presented model suggests a series combination of a defective and a nondefective region of the device's channel. It was found that the spreading of the damaged region along the channel from the drain toward the source is width dependent. In order to investigate that, devices with different channel widths were compared. By extracting and monitoring the electrical parameters in the linear regime of operation, after each stress cycle, the fitted results of the model were compared and evaluated.

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.

Novel F-Shaped Triple-Gate Structure for Suppression of Kink Effect and Improvement of Hot Carrier Reliability in Low-Temperature Polycrystalline Silicon Thin-Film Transistor

A novel F-shaped triple-gate device structure, which suppresses the kink effect of polycrystalline silicon (poly-Si) thin-film transistors (TFTs), was proposed and fabricated without any additional process. The proposed poly-Si TFT exhibits a lateral grain growth in a channel, as observed in the case of TFTs fabricated by sequential lateral solidification (SLS) or CW laser lateral crystallization (CLC). The entire current flow of the proposed device was strongly affected by grain boundaries of lateral grain growth. The F-shaped triple-gate structure consisted of one channel located parallel to the lateral grain growth direction and another channel located vertically to the lateral grain growth direction. It was verified that the proposed device could effectively reduce the kink current of poly-Si TFTs using the asymmetric mobility of the F-shaped gate structure by experiment and simulation. Our experimental results showed that the proposed F-shaped triple TFT could suppress the kink effect more effectively than conventional gate TFTs and then improve reliability under hot carrier stress condition.

The Characteristics of Hot-Carrier Stressed Bottom-Gate Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We have evaluated the reliability of the bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by employing alternating magnetic-field-enhanced rapid thermal annealing (AMFERTA) under the hot-carrier stress condition. The on-current was reduced due to the trap state creation caused by hot-electrons near drain junction. The off-current was suppressed due to the negative charge trapping near drain junction region. The temperature annealing after hot-carrier stress removed an amount of trap states in the drain junction. However, the tapped negative charges still remained near the drain junction. This charged region acts like lightly doped drain. Therefore, the sufficient annealing condition might be restored to the reduced on-current level without increasing off-current.

Investigation of hot carrier degradation in asymmetric nDeMOS transistors

Abstract Hot carrier degradation in asymmetric nDeMOS transistors is investigated in this paper. It is found that the worst case hot carrier stress condition in asymmetric nDeMOS transistors is at Ig,max, and not at Ib,max and hot-electron injection (HE, i.e. Vgs = Vds). Further, the damage regions in transistors upon various hot carrier stress modes are located by using variable amplitude charge pumping technique. It is found that the interface traps generation in the gate/n-type graded drain (NGRD) overlap and spacer/NGRD regions is the dominant mechanism of hot carrier degradation in transistors upon Ig,max stress mode. Moreover, both the interface trap generation and the electron trapping are two important factors to induce the electrical parameters shifts of asymmetric nDeMOS transistors under Ib,max and HE stress.