Hot Carrier Lifetime Research Articles

Hot carrier degradation and time-dependent dielectric breakdown in oxides

An overview is given of our present understanding of the main degradation mechanisms acting during hot carrier and high field stress of gate oxides. A brief summary of the most important charge injection mechanisms is given, followed by a description of the damage generated under uniform charge injection. Then the degradation under more realistic operating conditions of channel hot carrier injection is reviewed, including the lifetime determination methods and the strategies to improve the hot carrier lifetime. The most important methods of oxide breakdown testing are described, as well as the basics of oxide breakdown statistics. The change of this statistics with decreasing oxide thickness, and the impact on the reliability is illustrated. The most important breakdown models and field acceleration models are reviewed as well.

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

Abstract A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.

Remote plasma nitridation, deuterium anneal and pocket implant effects on NMOS hot carrier reliability

Abstract There are several advanced processes which are being actively studied as candidates for sub-0.25 μm technology. This paper studies the effects on NMOS hot carrier reliability from remote plasma nitrided oxide (RPNO), deuterium anneal and pocket implant. It is found that RPNO will not affect the SiO 2 /Si interface. The hot carrier reliability is better for the same device channel current. This is due to making the effective oxide thickness thinner and achieving the same drive current with longer channel length. The deuterium anneal can improve the hot carrier reliability, even with nitride sidewall, if proper annealing is done. While the pocket implant can reduce short channel effects, the hot carrier lifetime is degraded unless optimization is done.

Effect of statistical process variation of MOSFET on hot carrier lifetime

In this paper, we have investigated the effect of process variation on hot carrier reliability characteristics of MOSFET on 8-inch silicon wafer. We found a significant variation of hot carrier lifetime across the wafers due to gate length variation. Since the nonuniformity of gate length due to process variation is inevitable, it is necessary to consider enough margin of hot carrier lifetime. To optimize device performance in terms of driving current and reliability, the accurate evaluation of gate length variation is necessary.

Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates

The performance and reliability of NMOSFET asymmetric lightly doped drain (LDD) devices (with no LDD on the source side) are compared with those of conventional LDD devices. At a fixed V/sub dd/, asymmetric LDD devices exhibit higher I/sub dsat/ and shorter hot-carrier lifetime. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V/sub dd/ while higher I/sub dsat/ is retained. For the same hot-carrier lifetime, ring oscillators with NMOSFET asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power. The hot-carrier reliability of inverter, NAND, and NOR structures with asymmetric and conventional LDD devices is also simulated and compared.

Process stability of deuterium-annealed MOSFET's

Recent studies have shown improved NMOSFET transistor hot-carrier lifetime with the inclusion of a low-temperature post-metal anneal in a deuterium ambient. There have been few published results, however, on the optimization of the deuterium anneal or on the effect of further processing on deuterium-annealed samples. This paper reports the first results incorporating deuterium anneals at earlier steps in the process and the stability of the deuterium effect with further wafer processing. We also examine the effects of varying deuterium concentration in the anneal from 10 to 100% and annealing at different temperatures. Finally, the effect of combining a deuterium anneal with nitrided gate oxide is discussed.

Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems

This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal are still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes.

0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology

The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher I/sub dsat/ and larger I/sub sub/ TO maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V/sub dd/. For the same hot-carrier lifetime, we show that ring oscillators with asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power.

Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs

Hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action are thoroughly investigated in deep submicron N-channel SOI MOSFETs for a wide range of temperature and gate length. A multistage device degradation is highlighted for all the experimental conditions. Original V/sub t/ variations are also obtained for short-channel devices, a reduction of the threshold voltage being observed for intermediate values of stress time in the case of high stress drain biases. At low temperature (LT), an improvement of the device aging can be obtained in the low V/sub d/ range because of the significant reduction of the leakage current in the PBT regime. However, in the case of high V/sub d/, since the strong leakage current cannot be suppressed at LT, the device aging is larger than that obtained at room temperature. On the other hand, the device lifetime in off-state operation is carefully predicted as a function of gate length with various methods. Numerical simulations are also used in order to propose optimized silicon-on-insulator (SOI) architectures for alleviating the PBT action and improving the device performance and reliability.

Monitoring hot-carrier degradation in SOI MOSFETs by hot-carrier luminescence techniques

This paper addresses the problem of hot-carrier degradation and lifetime monitoring in SOI MOSFETs by means of hot-carrier-induced luminescence measurements. The peculiar emission behavior of SOI devices is clarified over a broad range of bias conditions by means of comparison with that of BULK MOSFETs. It is shown that detailed analysis of hot-carrier luminescence measurements at different photon energies provides a noninvasive monitoring tool for various aspects of degradation, such as worst case bias conditions, threshold voltage shift, and variations of the electric field and hot-carrier population in the damaged region. The measured light intensity represents also a sensitive acceleration factor for the extrapolation of lifetimes to real operating conditions.

Characterization of High Quality Nitrided Gate Dielectric Films Manufactured in Reduced Pressure Furnace for Ultralarge Scale Integration Complementary Metal Oxide Semiconductor Applications

High quality, ultrathin nitrided gate dielectric films were investigated to study their effects on device performance and reliability for ultralarge scale integration complementary metal oxide semiconductor applications. Thermal nitridation was performed on 200 mm wafers in a vertical reduced pressure furnace using and/or . It was demonstrated that nitrided gate dielectric films (ROXNOX, oxide) have improved hot carrier lifetime and barrier properties to boron diffusion. In addition, oxides, as well as ROXNOX, were found to be a promising alternative gate dielectric to the conventional oxide.

A comparison of hot-carrier degradation in tungsten polycide gate and poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n/sup +/ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi/sub x/ p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C/sub gd//sup s/ measurement shows increased susceptibility to electron trapping in the WSi/sub x/ device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on /spl Delta/V/sub t/=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 /spl mu/m, the reduced hot-carrier lifetime of WSi/sub x/ p-MOSFETs suggests that WF/sub 6/-based silicidation may not be appropriate for deep submicrometer CMOS devices.

Hot-carrier effects and reliable lifetime prediction in deep submicron N- and P-channel SOI MOSFETs

Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 /spl mu/m down to 0.1 /spl mu/m. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (V/sub g//spl ap/V/sub d/), maximum substrate current (V/sub g//spl ap/V/sub d//2) and parasitic bipolar transistor (PBT) action (V/sub g//spl ap/0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range.

Building-in reliability during library development: Hot-carrier degradation is no longer a problem of the technologists only!

Based on experimentally obtained data on different 0.35-μm CMOS technologies, hot-carrier (HC) degradation is shown to be one of the most critical reliability issues of this technology generation. By scaling the dimensions without scaling the power supply voltage, the transistor HC lifetime has decreased so severely that the conventional design-independent HC reliability requirements are no longer fulfilled. Therefore, the transistor HC performance needs to be taken into account already during the development of the standard library cells. In this paper, a case study will be presented that shows that building-in reliability during library developmen can relax the HC requirements during process qualification significantly while maintaining the product reliability.

Integration of Modified Plasma-Enhanced Chemical Vapor Deposited Tetraethoxysilane Intermetal Dielectric and Chemical-Mechanical Polishing Processes for 0.35 µm IC Device Reliability Improvement

The process of interlevel dielectrics (ILD) between poly-Si and metal is critical to device characteristics and reliability. Also, the shrinking design rules demand greater hot carrier reliability, which is strongly influenced by the ILD process. In this paper we describe a process for improving the reliability of 0.35 µ m devices by using modified plasma-enhanced chemical vapor deposited tetraethoxysilane (PECVD-TEOS) N2O-rich or O2-rich ILD films which contain less hydrogen concentration and excellent moisture resistance, and less mobile ion penetration after chemical-mechanical polishing (CMP), relative to standard PE-TEOS oxides. The hot carrier lifetime and the field isolation device threshold voltage are monitored and compared between devices with ILD layers based on different combinations of subatomespheric O3-TEOS borophosphorus silicate glass (BPSG), standard PE-TEOS, O2-rich and N2O-rich oxides. The material characteristics contributing to the reduction in post-CMP mobile ion levels and the improvement in device reliability will be discussed.

Hot-carrier reliability of non-degenerately doped tungsten polycide gate buried-channel p-MOSFETs

A polysilicon-depletion effect is observed for the non-degenerately doped polysilicon layer of a tungsten silicide-polysilicon gate stack of buried-channel p-MOSFETs, but not for n-MOSFETs with a polysilicon layer of the same doping concentration. A lower current drive and transconductance, coupled with a higher subthreshold slope, will result in poorer dynamic performance for p-MOSFETs having a lower doped polysilicon layer. The potential drop across the lower doped polysilicon layer results in lower gate currents. Consequently the p-MOSFETs with a lower doped polysilicon layer are more resistant to hot-carrier induced degradation and have higher hot-carrier lifetimes. Thus there exists an optimum polysilicon doping concentration for tungsten-polycide devices and the latter is dependent on the desired electrical performance and hot-carrier reliability of buried-channel p-MOSFETs.

Effects of hot-carrier degradation in analog CMOS circuits

In this paper a method is presented that allows to quantify the effects of hot carrier degradation on analog CMOS circuits. Specific features of hot carrier degradation related to analog CMOS operation are discussed in detail. On this basis single transistor stress experiments are defined monitoring analog operation and conclusions are drawn for the choice of analog hot carrier lifetime criteria. A general method is presented which establishes a relation between single transistor stress results and circuit parameter degradation. Examples for the applicability of this method are given, presenting measured data of hot-carrier-induced parameter shifts of analog sub-circuits.

A wafer level monitoring method for plasma-charging damage using antenna PMOSFET test structure

A novel monitoring method for plasma-charging damage is proposed. This method performs a quick and accurate evaluation using antenna PMOSFET. It was found that not only hot-carrier (HC) lifetime but transistor parameters such as initial gate current and substrate current were changed according to the degree of plasma-charging damage. However, the present work suggests that monitoring the shift of drain current after a few seconds of HC stress is a more accurate method to indicate plasma-charging damage. The monitoring method using the present test structure is demonstrated to be useful for realizing highly reliable devices.

An improved NMOS AC hot-carrier lifetime prediction algorithm based on the dominant degradation asymptote

This study presents a new algorithm for improved prediction of AC hot-carrier lifetime. It is based on identifying and projecting the dominant degradation asymptote. The algorithm accounts for the stress-bias dependence of the hot-carrier degradation rate and the nonlinearity of the degradation time-dependence. Detailed model parameter extraction and lifetime prediction procedures are explained, and applications of the new algorithm demonstrated. Significant differences in the predicted AC lifetimes are found between the existing and the new algorithms over a wide range of CMOS inverter design parameters, such as the input ramp rate and the load capacitance.

A method for the prediction of hot-carrier lifetime in floating SOI NMOSFETs

A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs.