NMOSFET Hot-carrier Degradation Research Articles

Hot-Carrier Degradation Modeling of Decananometer nMOSFETs Using the Drift-Diffusion Approach

We extend our previously suggested drift-diffusion (DD)-based hot-carrier degradation model to the case of decananometer transistors. Special attention is paid to the effect of electron-electron scattering, which populates the high energy tail of the carrier distribution function, by using a rate balance equation. We compare the results of the DD-based model with the results obtained from a spherical harmonics expansion of the Boltzmann transport equation as well as experimental data. We also study the accuracy and limits of the applicability of the DD-based model and conclude that this model is able to capture hot-carrier degradation in nMOSFETs over a range of gate lengths from 65 to 300 nm with excellent accuracy.

A Defect-Centric Analysis of the Temperature Dependence of the Channel Hot Carrier Degradation in nMOSFETs

The defect-centric distribution is used to study the temperature dependence of channel hot carrier (CHC) degradation in deeply scaled nMOSFETs. We analyze the temperature dependence in terms of the defect-centric parameters. The total number of traps is observed to increase with temperature, whereas the average threshold voltage shift produced by a single charged defect, i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\eta$</tex-math></inline-formula> , is confirmed to be independent of the temperature, as previously shown for bias temperature instability. By using the defect-centric analysis, we estimate the activation energy of the threshold voltage shift and that of the number of charged traps per device, which are directly linked to the CHC degradation.

Understanding and Modeling the Temperature Behavior of Hot-Carrier Degradation in SiON nMOSFETs

Using our physics-based model for hot-carrier degradation (HCD), we analyze the temperature behavior of HCD in nMOSFETs with a channel length of 44 nm. It was observed that, contrary to most previous findings, the linear drain current change ( $\Delta I_{\mathrm {d,lin}} $ ) measured during hot-carrier stress in these devices appears to be lower at higher temperatures. However, the difference between the $\Delta I_{\mathrm {d,lin}} $ values obtained at different temperatures decreases as the stress voltage increases. This trend is attributed to the single-carrier process of Si–H bond rupture, which is enhanced by the electron–electron scattering. We also consider another important modeling aspect, namely, the vibrational life-time of the Si–H bond, which also depends on the temperature. We finally show that our HCD model can successfully capture the temperature behavior of HCD with physically reasonable parameters.

Plasma Nitrided Oxide와 Thermally Nitrided Oxide를 적용한 NMOSFET의 Flicker Noise와 신뢰성에 대한 비교 분석

In this paper, flicker noise characteristic and channel hot carrier degradation of NMOSFETs with plasma nitrided oixde (PNO) and thermally nitrided oxide (TNO) are analyzed in depth. Compared with NMOSFET with TNO, flicker noise characteristic of NMOSFET with PNO is improved significantly because nitrogen density in PNO near the Si/ interface is less than that in TNO. However, device degradation of NMOSFET with PNO by channel hot carrier stress is greater than that with TNO although PMOSFET with PNO showed greater immunity to NBTI degradation than that with TNO in previous study. Therefore, concurrent investigation of the reliability as well as low frequency noise characteristics of NMOSFET and PMOSFET is required for the development of high performance analog MOSFET technology.

NMOSFET의 Hot-Carrier 열화현상

본 논문에서는 아날로그 회로에 사용되는 NMOSFET에 대한 Hot-Carrier 열화특성을 조사하였다. 여러 값을 갖는 게이트 전압으로 스트레스를 인가한 후, 소자의 파라미터 열화를 포화 영역에서 측정하였다. 스트레스 게이트 전압의 범위에 따라 계면 상태(interface state) 뿐 아니라 전자와 정공의 포획이 드레인 근처 게이트 산화막에서 확인되었다. 그리고 특히 낮은 게이트 전압의 포화영역에서는 정공의 포획이 많이 발생하였다. 이러한 전하들의 포획은 전달 컨덕턴스 (<TEX>$g_m$</TEX>) 및 출력 컨덕턴스 (<TEX>$g_{ds}$</TEX>)의 열화의 원인이 된다. 아날로그 동작 범위의 소자에서 파라미터 열화는 소자의 채널 길이에 매우 민감하게 반응한다. 채널길이가 짧을수록 정공 포획이 채널 전도도에 미치는 영향이 증가하게 되어 열화가 증가되었다. 이와 같이 아날로그 동작 조건 및 아날로그 소자의 구조에 따라 <TEX>$g_m$</TEX> 및 <TEX>$g_{ds}$</TEX>의 변화가 발생하므로 원하는 전압 이득(<TEX>$A_V=g_m/g_{ds}$</TEX>)을 얻기 위해서는 회로 설계시 이러한 요소들에 대한 고려가 필요하다. This study has provided some of the first experimental results of NMOSFET hot-carrier degradation for the analog circuit application. After hot-carrier stress under the whole range of gate voltage, the degradation of NMOSFET characteristics is measured in saturation region. In addition to interface states, the evidences of hole and electron traps are found near drain depending on the biased gate voltage, which is believed to the cause for the variation of the transconductance(<TEX>$g_m$</TEX>) and the output conductance(<TEX>$g_{ds}$</TEX>). And it is found that hole trap is a dominant mechanism of device degradation in a low-gate voltage saturation region, The parameter degradation is sensitive to the channel length of devices. As the channel length is shortened, the influence of hole trap on the channel conductance is increased. Because the magnitude of <TEX>$g_m$</TEX> and <TEX>$g_{ds}$</TEX> are increased or decreased depending on analog operation conditions and analog device structures, careful transistor design including the level of the biased gate voltage and the channel length is therefore required for optimal voltage gain (<TEX>$A_V=g_m/g_{ds}$</TEX>) in analog circuit.

Impacts of SiN-Capping Layer on the Device Characteristics and Hot-Carrier Degradation of nMOSFETs

Impacts of silicon nitride (SiN)-capping layer and the associated deposition process on the device characteristics and hot-electron degradation of nMOSFETs are investigated in this paper. The SiN layer used to induce channel strain for mobility enhancement was deposited by a low-pressure chemical vapor deposition. The deposition of the SiN aggravates threshold-voltage roll-off due to additional thermal budget and the strain effect. It is also found that the device hot-electron degradation is worse with the addition of the SiN capping. Furthermore, our results indicate that both the bandgap narrowing caused by the channel strain and the abundant hydrogen species from the precursors of SiN deposition contribute to the aggravated hot-electron effect.

Channel width dependence of NMOSFET hot carrier degradation

The channel width dependence of hot carrier reliability on NMOSFETs from 0.4-/spl mu/m to 0.13-/spl mu/m technology has been studied at both I/sub b,peak/ and V/sub g/ = V/sub d/ conditions. Enhanced degradation on narrow width devices happens on most technologies. The I/sub b//I/sub d/ value and vertical electric field are proposed to be the reasons for enhanced degradation on narrow width NMOSFETs.

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

Enhanced hot carrier degradation in nMOSFETs with a forward substrate bias is observed. The degradation cannot be explained by conventional channel hot electron effects. Instead, an Auger recombination-assisted hot electron process is proposed. In the process, holes are injected from the forward-biased substrate and provide for Auger recombination with electrons in the channel, thus substantially increasing channel hot electron energy. Measured hot electron gate current and the light emission spectrum provide evidence that the high-energy tail of channel electrons is increased with a positive substrate bias. The drain current degradation is about ten times more serious in forward-biased substrate mode than in standard mode. The Auger-enhanced degradation exhibits positive temperature dependence and may appear to be a severe reliability issue in high temperature operation condition.

Matching behaviours of analogue NMOSFET parameters under hot-carrier stress

In this paper, we provide some experimental results of NMOSFET hot-carrier degradation for analogue circuit application. After hot-carrier stress, over the whole range of gate voltages, the drain current mismatch and output conductance are measured in the saturation region. Evidence of hole and electron trapping is found near the drain under low and high biased gate voltages, respectively, which is believed to be the cause of the variation of the output conductance during stress. Under low-gate-voltage stress, acceptor-like interface traps are also generated and compensate for the influence of trapped holes.

A new lifetime prediction method for hot-carrier degradation in n-MOSFETs with ultrathin gate oxides under Vg= Vd

Hot-carrier degradation of n-MOSFETs at high gate voltages ( V g= V d) is examined. A new lifetime prediction method is developed based on the universal power law between the degradation of saturated drain current (d I dsat) and the product of the injected charge fluence times the gate current, which is independent of gate or drain voltages. This method is applied to 4 and 5 nm n-MOSFETs and lifetimes are estimated under their operation conditions. It is applicable to n-MOSFETs with ultrathin gate oxides.

A unified understanding on fully-depleted SOI NMOSFET hot-carrier degradation

A unified understanding on fully-depleted SOI (FDSOI) N-Channel MOSFET hot-carrier degradation is presented using a novel methodology and devices fabricated on SIMOX and BESOI substrates. We measured traditionally reported front gate threshold voltage shift and de-coupled front and back gate threshold voltage shifts by accumulating the opposite interface. Interpretation of the experimental results are provided on floating body, bipolar breakdown and series parasitic source/drain resistance (R/sub ds/) debiasing effects on hot-carrier degradation. BESOI substrates showed less degradation than SIMOX. However, the degradation mechanisms are same in both substrates. At low drain bias, device degradation is dominated by the coupling of back interface degradation to the front interface. Back interface is degraded by the hole trapping and interface states generation simultaneously. Front interface is degraded by the interface states generation. At moderate drain bias, floating body induced shift in threshold voltage is dominant despite moderate front interface states generation. At high V/sub ds/, interface states generation at the back interface and the competing hole trapping and interface states generation at the front interface are observed. Finally, we proposed a phenomenological model for FDSOI N-Channel MOSFET degradation taking into account all dominant effects.

The impact of NMOSFET hot-carrier degradation on CMOS analog subcircuit performance

This study presents some of the first experimental data on the impact of NMOSFET hot-carrier-induced degradation on CMOS analog subcircuit performance. Because of circuit design requirements, most NMOSFET's used for analog applications are biased in the saturation region with a low gate-to-source voltage. Under such operating conditions, in addition to interface states, significant numbers of hole traps are also generated inside the gate oxide. Because acceptor-type interface states are mostly unoccupied in the saturation region, hole traps are found to have a much more significant impact on analog NMOSFET device performance. The hot-carrier-induced degradation of analog subcircuit performance is also found to be quite sensitive to the particular circuit design and operating conditions. Circuit performance and reliability tradeoffs are examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

How do hot carriers degrade n-channel MOSFETs?

Explores the mechanisms of hot carrier degradation in n-MOSFETs. In addressing the problem of hot carrier degradation, we examine the carrier injection process, whereby electrons and holes are injected into the oxide from the channel. Next, we'll look at the processes responsible for creating damage. Third, the impact of the damage on the MOSFET's terminal characteristics is deternined. Then the damage process is modeled. Finally, we'll address ways to reduce hot carrier degradation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Photon spectrum analysis of hot carrier degradation in NMOSFETS

The photon spectrum is analysed for two types of LDD n-MOSFET. It is found that at a special wavelength the photon spectrum has close correlation with the degradation rate of transconductance or Vt shifts, independent of device sizes and stress conditions. Photon spectrum analysis is found to be an effective monitor for the hot carrier degradation.

Hot carrier degradation in n-MOSFETs used as pass transistors

The hot carrier properties of n-MOS devices in the pass transistor mode are examined. In this mode, damage occurs at both source and drain junctions of the transistor. It is shown that the damage at each junction proceeds independently, and that the damage at each junction is additive. It is found, consequently, that the pass transistor is more sensitive to hot carrier damage than a transistor in the inverter mode, with lifetimes based on the linear region g/sub m/ change being 3-4 times lower. Using a saturated current (I/sub dsat/) definition, the lifetimes for pass transistors can be about an order of magnitude lower than for transistors operated in only one source/drain orientation, assuming similar voltage conditions. About half of this reduction in lifetime is because degradation occurs at both junctions, and the other half is due to the fact that degradation at the source junction causes a much more dramatic effect upon I/sub dsat/ than damage at the drain junction.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>