Heterogeneous integration enables high-density integration to improve system functionality, but meanwhile brings reliability concerns due to the intensification of temperature and thermal stress. However, research on thermal stress effects in nanoscale transistors within heterogeneous integrated circuit is still very limited up to now. Multiphysics computation for the heterogeneous integration of nanoscale p-FinFET with GaN high electron mobility transistor (HEMT) on silicon substrate is performed. Firstly, self-heating of GaN HEMT induced thermal stress is simulated. Then, thermal stress effects induced by the GaN HEMT on quantum transport in the FinFET at different locations are compared and analyzed, including the hole effective mass, hole average velocity, on/off-state current, and on-off ratio. Moreover, the impacts of crystal orientation configurations are further discussed. Simulation results show that the impact of thermal stress on FinFET is highly dependent on the Si crystal orientation and its location relative to GaN HEMT. Taking the FinFET with (001)/[110] confinement/transport orientation, which is at a distance of RFET and an angle of φ from the GaN HEMT as an example, thermal stress induces the significant reductions in Ion and Ioff of FinFET at φ = π/2 and φ = 3π/2, and the increases of Ion and Ioff in FinFET at φ = 0 and φ = π, but has small impact on FinFETs located diagonally to the GaN HEMT.